Designing a Hybrid Digital / Analog Quantum Physics Emulator as Open Hardware

arXiv:2302.00821 · quant-ph · Submitted 2023-02-02 · Read on arXiv

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Introduction to the show: ident: Quantum Radio. Generated commentary on the latest quantum physics and condensed matter papers.

Kai: I'm Kai.

Mira: And I'm Mira, here with Lev.

Kai: We're looking at the paper: "Designing a Hybrid Digital / Analog Quantum Physics Emulator as Open Hardware".

Mira: Here's the gist of the paper. The gist Designing a Hybrid Digital/Analog Quantum Physics Emulator as Open Hardware introduces a new scheme for representing quantum information using analog signals to lessen bandwidth limitations in existing classical electronic hardware emulators.

Kai: This approach aims to achieve competitive performance against FPGA-based emulators by shifting the scaling problem from time and space to the precision and settling times of analog modules.

Mira: Naive Hardware Scaling Problem The naive approach involves mapping identification numbers for quantum states directly to a set of simple sinusoidal analog signals, where the complexity scales as: c = 2 · rank(M) + rank(W) − 1 (Page 3).

Kai: This yields an expression of the complexity C of a direct and purely hardwarebased implementation of a simplified state emulation that behaves in the way that K has been described (Page 3).

Paper summary: Kai: So we're looking at this paper, "Designing a Hybrid Digital / Analog Quantum Physics Emulator as Open Hardware". It looks like the main idea is they’re trying to fix the scaling issues in classical hardware emulators by using analog signals.

Mira: Yeah, they're proposing a way to represent quantum information using those analog signals that cuts down on the bandwidth limitations you see in current approaches in certain regimes <ref:2302.00821#pg1>.

Lev: It’s about taking full advantage of how analog signals can encode information using RMS voltage along with frequency and phase <ref:2302.00821#pg1>. I mean, the authors introduce a mathematical framework that separates the information needed for measurement in the computational basis from the stuff that isn't relevant to it <ref:2302.00821#pg1>.

Kai: And they build circuits that use this separation of concerns to simplify things when you're working with quantum information in this new representation <ref:2302.00821#pg1>. It sounds like they’re trying to make the process of working with these states much less complicated for the hardware <ref:2302.00821#pg1>.

Mira: The paper claims that it's comparatively very inexpensive, as low as a dollar and a half per qubit in some cases <ref:2302.00821#pg1>. They argue this approach can outmatch the computing capabilities of existing FPGA based emulators thirty-eight <ref:2302.00821#pg1,outmatch the computing capabilities of existing FPGA based emulators 38>.

Lev: But they also admit that scaling beyond tens of qubits is still impractical because of the constraints on analog hardware module precision <ref:2302.00821#pg76>. That's a big limitation for any real-world implementation, right?

Kai: Exactly. So what we’re hearing from this paper is that they are shifting the scaling problem away from time and space and towards the precision and settling times of analog modules <ref:2302.00821#pg35>. That’s a shift in focus for hardware development <ref:2302.00821#pg35>.

Mira: They start by looking at the naive approach where you map identification numbers for quantum states directly to simple sinusoidal analog signals, which scales with complexity C being three times two to the Q minus one, or three times two to the Q minus one <ref:2302.00821#pg3>. This shows how hard a direct implementation is in terms of hardware resources <ref:2302.00821#pg4>.

Lev: That complexity expression, C being three times two to the Q minus one, shows that directly simulating this simplified qubit state scales in hardware resources with O(two n) <ref:2302.00821#pg4>. That’s exponential scaling we’re trying to avoid <ref:2302.00821#pg4>.

Kai: Before this paper, the bandwidth limitation problem was a big one because representing an n qubit state with a complex oscillating time-domain signal means the number of qubits you can actually encode is limited by what the equipment can handle <ref:2302.00821#pg5>.

Paper summary: Mira: The La Cour and Ott scheme, for example, requires components like "two analog sources, two quadrature multiplier circuits, one phase shift circuit, and one bandpass filter" just to model a general single qubit state <ref:2302.00821#pg4>. That methodology scales with untenable complexity because it’s constrained by exponential scaling of required bandwidth <ref:2302.00821#pg5>.

Lev: So they propose this dual oscillator representation scheme to overcome those bandwidth limits, characterized by the property that a pair of oscillators must be sufficient to emulate n superimposed states <ref:2302.00821#pg6>. They use a probabilistic state with n observable values modeled by a probability simplex, and the Bloch sphere gives them a more true representation of a qubit state <ref:2302.00821#pg6>.

Kai: How do they break down the quantum state coefficients? The paper says each one is broken into three pieces: "Whether the coefficient is real or imaginary, Whether the coefficient is positive or negative, and The magnitude of the coefficient" <ref:2302.00821#pg7>. That seems like a pretty detailed way to handle it <ref:2302.00821#pg7>.

Mira: The core of this scheme involves mapping a set of quadratic relationships to a set of Cauchy sequences of angular values, which are then mapped to practically realizable frequencies <ref:2302.00821#pg10>. This measurable value is called the Higher Dimensional Observable, or HDO, because it’s a proxy for us to measure information in a higher dimensional space <ref:2302.00821#pg10>.

Lev: The HDO has to have n equal to two to the Q observable states, similar to the energy eigenstates of the quantum harmonic oscillator <ref:2302.00821#pg11>. The HDO shows up as a frequency, and its strength is equivalent to its probability of being consistently measured by a frequency measurement device <ref:2302.00821#pg12>.

Kai: So how does this translate into physical hardware? They utilize High Speed Analog Modules, or HSAMs, to convert parameters 'a' and 'g' into phi <ref:2302.00821#pg30>. These modules involve sequential steps like "setting the voltage V1, one half of the value of one in the desired numerical precision of the analog calculation module" <ref:2302.00821#pg35>.

Mira: The total time required to update a state is given by t tot equals one scalable time unit plus fifty nanoseconds plus Vxd minus delta minus Vxzero microsecond <ref:2302.00821#pg35>. And the speed of any quantum operation applied by this module is directly proportional to "the speed of the voltage sweep from Vx equal to Va to Vx equal to two times a minus one V1 over two" <ref:2302.00821#pg34>.

Lev: That speed relationship is key, it means how fast you can do an operation depends on the voltage sweep rate <ref:2302.00821#pg34>. They also encode the sign and phase information into the same signal as the probability distribution of a state’s observables by oscillating the frequency output omega from the AX7MAF1 high frequency oscillator <ref:2302.00821#pg36>.

Paper summary: Kai: That oscillation allows them to encode two to 2Q plus one separate phases in the frequency of the output oscillation, and this can be measured within a time frame between two to 2Q plus one over fifty megahertz and two to 2Q plus one over two point one gigahertz <ref:2302.00821#pg38>.

Mira: They also looked at an alternative hybrid analog digital approach where you apply operations to each ket individually using linear theory, which guarantees that when an operation multiplies the state by i, "a few things happen" <ref:2302.00821#pg40>. This involves swapping strengths between oscillator modules and updating the sign bit associated with the first part <ref:2302.00821#pg40>.

Lev: They use a Very Long Instruction Word, or VLIW architecture, to manage instruction scheduling, which separates digital and analog execution steps to keep the order of operations correct <ref:2302.00821#pg63>. That separation is important for making sure the quantum operations actually happen in sequence <ref:2302.00821#pg63>.

Kai: So what does this mean for practical use? The paper says the upper bound on representable qubits is Q equal to log of four million five hundred eighty thousand over log of two, which is twenty-two qubits with the AX7MAF1 <ref:2302.00821#pg41>. And the low-end cost per qubit is roughly one dollar and a half, while the high-end cost per qubit is approximately sixty three dollars and twenty five cents <ref:2302.00821#pg41>.

Mira: The paper concludes that this approach partially overcomes the exponential scaling issue by encoding information in an RMS voltage intermediately instead of a frequency, using the frequency domain only for encoding the phase component of the state <ref:2302.00821#pg76>. They say the frequencies used are derived via a mathematical framework inspired by the quantum harmonic oscillator to ensure they exist in a hierarchy that is optimal <ref:2302.00821#pg76>.

Lev: The main limitation they flag is that scaling beyond tens of qubits remains impractical because of constraints on analog hardware module precision <ref:2302.00821#pg76>. So, this scheme stops working where the analog hardware can't maintain the necessary accuracy for larger systems <ref:2302.00821#pg76>.

Kai: So, to sum up on "Designing a Hybrid Digital / Analog Quantum Physics Emulator as Open Hardware", they introduce a new way to use analog signals, using RMS voltage and frequency and phase <ref:2302.00821#pg1>. They separate the relevant measurement information from irrelevant information <ref:2302.00821#pg1>.

Mira: The implication is that it’s a relatively inexpensive way to compete with FPGA emulators, even if we can only realistically build systems up to about twenty two qubits <ref:2302.00821#pg41>. It opens up a new direction by focusing on improving analog electronic circuit performance <ref:2302.00821#pg76>.

Lev: So for the listener, it means that while we can't build huge quantum computers with this specific approach yet, the path forward might involve making those analog components more precise and faster <ref:2302.00821#pg76>. That's where real hardware improvements need to happen if we want to move past the NISQ regime <ref:2302.00821#pg76>.

Conclusion: Kai: So we’re wrapping up our look at this paper, "Designing a Hybrid Digital / Analog Quantum Physics Emulator as Open Hardware". Basically, they figured out a new way to handle quantum information using analog signals instead of just pure digital stuff.

Mira: Right. They took the scaling problem—that exponential explosion in required resources—and tried to move it somewhere else, away from time and space and toward how precise the analog hardware can actually be.

Lev: From my side, it’s interesting because they’re talking about circuits that use RMS voltage and frequency to represent states, which is a totally different kind of physical reality than what we usually build on FPGAs.

Kai: Yeah, I'm curious about the actual numbers they came up with. The paper claims this approach can be cheap enough to beat FPGA emulators in terms of performance per qubit, even if it’s not scalable for huge systems yet.

Mira: That’s what they say, and I think that’s the key point: you can get competitive results by focusing on better analog circuit design instead of just throwing more digital gates at a problem.

Lev: But the caveat is real, right? They explicitly state that scaling past tens of qubits is still out of reach because you run into precision limits in those analog modules.

Kai: So what does this mean for us building real quantum hardware? It suggests that improving the performance and settling times of analog components might be a more practical way to push the limits than just trying to invent bigger digital chips.

Mira: Exactly. It opens up a new avenue where classical simulators can improve by getting better at making those analog electronic circuits work correctly for quantum physics.

Lev: We need to see if we can translate that "improving analog circuit performance" idea into actual, measurable gains on real hardware platforms, not just theoretical models.

Marcus Edwards

quant-ph

Submitted: 2023-02-02

Updated: 2026-10-18

Comments: Updated with minor corrections, clarifications

License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/

Importance score: 75/100

The gist: The gist Designing a Hybrid Digital/Analog Quantum Physics Emulator as Open Hardware introduces a new scheme for representing quantum information using analog signals to lessen bandwidth limitations

Key concepts

Naive Hardware Scaling Problem: Directly mapping quantum state IDs to simple sinusoidal signals leads to complexity scaling as C = 3 * 2^Q - 1. This means the hardware resources needed grow exponentially with the number of qubits (Q), making direct simulation impractical for large systems.
Bandwidth Limitation Problem: Existing signal-based methods are constrained because representing an n-qubit state requires complex oscillating time-domain signals, limiting how many qubits can be encoded by the available bandwidth. This scaling is untenable for general quantum states.
Higher Dimensional Observable (HDO): The HDO is a measurable value derived from mapping quadratic relationships to Cauchy sequences of angular values, which are then converted into practical frequencies. It acts as a proxy for measuring information in a higher-dimensional space, where its strength relates to the probability of consistent measurement.
Dual Oscillator Representation Scheme: This scheme overcomes bandwidth issues by using a pair of oscillators sufficient to emulate n superimposed states. It represents quantum state coefficients by breaking them into real/imaginary parts and positive/negative signs, encoding information via RMS voltage and frequency.

Terminology

Quantum Physics — 1× in this paper · explained in 12 episodes

Summary

The gist Designing a Hybrid Digital/Analog Quantum Physics Emulator as Open Hardware introduces a new scheme for representing quantum information using analog signals to lessen bandwidth limitations in existing classical electronic hardware emulators. This approach aims to achieve competitive performance against FPGA-based emulators by shifting the scaling problem from time and space to the precision and settling times of analog modules.

Naive Hardware Scaling Problem

The naive approach involves mapping identification numbers for quantum states directly to a set of simple sinusoidal analog signals, where the complexity scales as: c = 2 · rank(M) + rank(W) − 1 (Page 3). This yields an expression of the complexity C of a direct and purely hardwarebased implementation of a simplified state emulation that behaves in the way that K has been described (Page 3). The complexity for multi-qubit states is expressed as C = 3 · 2 Q − 1 where Q is the number of qubits (Page 3). This expresses the fact that the task of directly simulating this simplified qubit state scales in hardware resources with O(2n) (Page 4).

Bandwidth Limitation Problem

Existing signal-based emulation approaches suffer from a fundamental bandwidth limitation because a quantum state of n qubits is represented using a complex oscillating time-domain signal, and the number of qubits that can be encoded is limited by the attainable bandwidth (Page 5). The La Cour and Ott scheme requires components such as 2 analog sources, 2 quadrature multiplier circuits, 1 phase shift circuit, and 1 bandpass filter to model a general single qubit state (Page 4). This methodology scales with untenable complexity because it is constrained by exponential scaling of required bandwidth (Page 5).

Dual Oscillator Representation Scheme

To overcome bandwidth limitations, the paper proposes a new scheme characterized by several properties: A pair of oscillators must be sufficient to emulate n superimposed states (Page 6). The representation uses a probabilistic state with n observable values modeled by a probability simplex, and the Bloch sphere provides a more true representation of a qubit state (Page 6). Each coefficient in the equation for a quantum state is broken into three pieces: Whether the coefficient is real or imaginary, Whether the coefficient is positive or negative, and The magnitude of the coefficient (Page 7).

Higher Dimensional Observable (HDO)

The core of this scheme involves mapping a set of quadratic relationships to a set of Cauchy sequences of angular values, which are then mapped to practically realizable frequencies (Page 10). This measurable value is called the Higher Dimensional Observable (HDO) since it is a proxy for us to measure information in a higher dimensional space (Page 10). The HDO must have n = 2 Q observable states, analogous to the energy eigenstates of the quantum harmonic oscillator (Page 11). The HDO is manifested as a frequency, and its strength is equivalent to its probability of being consistently measured by a frequency measurement device (Page 12).

Dual Oscillator Electrical Implementation Design

The system utilizes High Speed Analog Modules (HSAMs) to convert the parameters a, g to phi (Page 30). The HSAM involves sequential steps including Setting the voltage V1, one half of the value of 1 in the desired numerical precision of the analog calculation module (Page 30). The total time required to update the state is given by ttot = 1 scalable time unit + 50ns + (Vxd − ∆ − Vx0)µs (Page 35). The speed of any quantum operation applied by this module is directly proportional to The speed of the voltage sweep from Vx = Va to Vx = 2(a − 1)V1/2 (Page 34).

Probabilistic Measurements and Encoding Sign and Phase

The probability of measuring a particular value of a in terms of the strength of the HDO is expressed as p(a, g) = δ(a, g)/σ(a, g) (Page 23). The sign and phase information are encoded into the same signal as the probability distribution of a state’s observables by oscillating the frequency output ω from the AX7MAF1 high frequency oscillator (Page 36). This allows for encoding 2(2Q+1) separate phases in the frequency of the output oscillation, which can be measured within a time frame between 2(2Q+1)/50MHz and 2(2Q+1)/2.1GHz (Page 38).

Alternative Hybrid Analog / Digital Approach

An alternative approach uses linear theory to apply operations to each ket individually, which guarantees that when an operation has the effect of multiplying the state ⃗b⟩ by i, a few things happen (Page 40). This involves swapping strengths between oscillator modules and updating the sign bit associated with the first (Page 40). The system uses a Very Long Instruction Word (VLIW) architecture to manage instruction scheduling, separating digital and analog execution steps to maintain the order of operations (Page 63).

Capabilities and Limitations of the Scheme

The upper bound on representable qubits is Q = log(4580000)/log(2) = 22 qubits with the AX7MAF1 (Page 41). The low-end cost per qubit is roughly a dollar and a half, while the high-end cost per qubit is approximately sixty-three dollars and twenty-five cents (Page 41). Scaling beyond tens of qubits remains impractical due to constraints of analog hardware module precision (Page 76).

Conclusions

The approach partially overcomes the exponential scaling issue by encoding information in an RMS voltage intermediately instead of a frequency, using the frequency domain at this stage only for encoding the phase component of the state (Page 76). The frequencies used to represent the quantum state are derived via a mathematical framework inspired by the quantum harmonic oscillator to ensure that they exist in a hierarchy that is in a sense optimal (Page 76). It is comparatively inexpensive to outmatch existing FPGA based emulators, though scaling beyond tens of qubits is still impractical due to constraints of analog hardware module precision (Page 76).

Paper author contributions

Marcus Edwards designed and documented the emulator as well as performed the related proof of concept experiments before finally writing the paper (Page 78).

Acknowledgments

Thanks to Dr. Shohini Ghose of Wilfrid Laurier University for helpful discussions on early versions of this work (Page 78).

References

[1] IEEE Standard VHDL Language Reference Manual. [1] IEEE Standard VHDL Language Reference Manual.

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[4] Alliance Memory AS6C6264 Datasheet, March 2009. [4] Alliance Memory AS6C6264 Datasheet, March 2009.

[5] Texas Instruments LMV771 Datasheet, September 2010. [5] Texas Instruments LMV771 Datasheet, September 2010.

[6] Integrated Silicon Solutions IS62WV12816ALL Datasheet, November 2013. [6] Integrated Silicon Solutions IS62WV12816ALL Datasheet, November 2013.

[7] Texas Instruments LMH3401 Op Amp Datasheet. December 2014. [7] Texas Instruments LMH3401 Op Amp Datasheet, December 2014.

[8] Analog Devices ADL5569 Datasheet. 2018. [8] Analog Devices ADL5569 Datasheet, 2018.

[9] Abracon AX7 Series Datasheet. April 2019. [9] Abracon AX7 Series Datasheet, April 2019.

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[13] Maher Ahmed. Analog 1 at wilfrid laurier university. Undergraduate course, 2016. [13] Maher Ahmed, Analog 1 at wilfrid laurier university, Undergraduate course, 2016.

[14] Abdullah Ateş, Barış Baykant Alagöz, Celaleddin Yeroğlu, and Hafız Alisoy. Sigmoid based PID controller implementation for rotor control. In 2015 European Control Conference (ECC), pages 458–463, July 2015. [14] Abdullah Ateş, Barış Baykant Alagöz, Celaleddin Yeroğlu, and Hafız Alisoy. Sigmoid based PID controller implementation for rotor control.

Improvements for AI systems

We can improve AI systems by shifting scaling limits from time (in terms of runtime on a CPU or in a way that is limited by bandwidth) to the time of analog modules’ settling times and space in terms of the precision of available analog modules. This allows for emulation capabilities that are computationally inexpensive compared to digital FPGA emulators, as the paper argues it is comparatively very inexpensive (as low as 5.00 / qubit) to outmatch the computing capabilities of existing FPGA based emulators [38].
The improved AI system can perform quantum state emulation using a hybrid digital/analog architecture that encodes quantum information using analog signals that lessens the bandwidth limitation problem (in certain regimes) seen in existing approaches by taking full advantage of the ability of analog signals to encode information using RMS voltage as well as frequency and phase.
The system can achieve probabilistic measurements by mapping the state to a Higher Dimensional Observable (HDO), which is defined as a proxy for measuring information in a higher dimensional space, allowing the system to represent pure quantum states only through geometric representations like the Bloch sphere.
The AI can implement complex quantum operations like Pauli matrices using control systems inspired by the quantum harmonic oscillator, where an operation is equivalent to a convolution product CP of two functions of time, enabling an efficient execution model that maintains the order of operations.
The system can utilize a VLIW architecture for digital microprocessing, which allows for instruction level parallelism and out-of-order execution by scheduling analog and digital operations separately, ensuring that the system achieves sequential instruction level parallelism while maintaining the order of operations.

Sources

Signal-based classical emulation of a universal quantum computer