DC Cryogenic Modeling of Open-Source SkyWater 130 nm MOSFETs at 77 K Using BSIM4

The gist The work presents the first systematic DC characterization and open-source BSIM4-based isothermal model of SKY130 MOSFETs at 77 K, which is a promising candidate for liquid argon detectors in high-energy physics applications.

Cryogenic Modeling Approach

The researchers developed a cryogenic modeling approach to produce a SPICE-compatible, isothermal BSIM4-based model for select transistor sizes at 77 K The methodology involves changing the model parameter TNOM from its default, room temperature value to 77 K (−196.15°C) This parameter identifies the temperature at which the PDK was originally validated, which is 30°C in the case of SKY130. A physics-based parameter extraction strategy is devised, guided by prior BSIM4 cryogenic modeling efforts Only DC characteristics are used because previous C–V studies in advanced CMOS nodes suggest that the dominant low-temperature effect on intrinsic gate-capacitance (CGG) characteristics is often a shift in the bias axis associated with VTH (T). The Synopsys tool, MysticTM (Version 2023.12), is utilized to perform parameter extraction This tool allows for target data, simulated model data, parameter sets, and select I–V curve(s) to target for extraction as inputs for an extraction stage and seeks to find optimal solutions by adjusting specified model parameters to achieve best fit of the target data and model I–V curves.

Key Transistor Parameters at 77 K

The paper characterizes several key transistor parameters that change with temperature, including:

1. Threshold Voltage (VTH): Previous studies show that the MOSFET threshold voltage generally increases as temperature decreases At cryogenic temperatures, however, the threshold voltage shift cannot be described only by the conventional complete-ionization form. Bandgap widening produces an additional upward shift in VTH In our parameter extraction methodology, VTH0 serves as the reference parameter that mainly captures the measured shift in VTH between 300 K and 77 K.

2. Carrier Mobility (μ): At low temperature, the mobility cannot be described reliably by a simple roomtemperature extrapolation The effective mobility may be written using Matthiessen’s rule as 1/μeff = 1/μph + 1/μC + 1/μsr As the temperature is reduced, phonon scattering weakens and tends to increase μeff.

3. Subthreshold Swing (SS): The transistor behavior in the subthreshold operating region is described by the subthreshold swing (SS) parameter Under the classical Boltzmann picture, the subthreshold swing is given by SS = n / kB T ln(10). For operation near 77 K, this thermal scaling provides a reasonable first-order description of experimental behavior.

4. On-State Current (Ion): Ion is influenced by two competing trends: the increase in threshold voltage (Section 2.1.1) and the increase in carrier mobility (Section 2.1.2). In BSIM4, Ion is obtained from the unified drain-current model described in Chapter 5 of Ref [20].

5. Drain-to-Source Series Resistance (Rs d): For transistors with lightly doped drain (LDD) extensions, an additional cryogenic mechanism must be considered Near cryogenic temperatures, the total series resistance can reflect two opposite trends: a decrease of the heavily doped source/drain parasitic resistance with decreasing temperature, and an increase of the lightly doped extension resistance due to freeze-out.

6. Drain-Induced Barrier Lowering (DIBL): DIBL is a short-channel effect in which an increase in drain bias lowers the source-channel potential barrier Within the BSIM4 framework, ETA0 is the primary DIBL coefficient in the subthreshold region.

Modeling Results and Accuracy

The researchers employed a per-bin extraction strategy applied to measured 77 K output and transfer characteristics This resulted in eighteen distinct cryogenic models at 77 K spanning the measured nMOS and pMOS geometries. The resulting models improve agreement with measured 77 K device behavior relative to the room-temperature PDK, with average errors on the order of 20% in relative RMS and no strong dependence on drain bias. The RRMS error is used to summarize the agreement between the measured and simulated drain current Smaller values of RRMS indicate better overall agreement, and smaller values of sigmaRRMS indicate more uniform model accuracy across the set of measured curves. No dependence of the absolute error on the drain-to-source voltage bias applied for each ID–VG S curve was observed, indicating the model achieves sufficiently accurate representation of device behavior across model bins.

Conclusion

This work establishes SKY130 as a practical open-source node for 77 K cryogenic circuit design in high-energy physics and related low-temperature instrumentation applications. The developed models are NGSpice-compatible and publicly available on GitHub [34]. Future work will extend the model across additional cryogenic temperatures and broader geometry coverage toward a temperature- and geometry-dependent cryogenic PDK.

A Error Tables Table 5 lists reported errors for 300 K models for select transistor sizes, while Table 6 reports errors for developed 77 K models for select transistor sizes. The average relative RMS error on the order of 20% is reported in the conclusion. The work is limited to DC isothermal modeling and does not yet include noise, capacitance, and has not yet experimentally validated mismatch or process corner variations.

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Prepared for submission to JINST DC Cryogenic Modeling of Open-Source SkyWater 130 nm MOSFETs at 77 K Using BSIM4 F. Beall1, A. Rimal1, O. Seidel1, Y. Mei1, A. D. McDonald3, I. Parmaksiz5,1 V. A. Chirayath1, J. Asaadi1, D. Braga2, J. B. R Battat4

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Contents 1 Introduction Open-source process design kits (PDKs), which are open-source libraries made available by the semiconductor foundry that model the fabrication process and the variations there-in, offer a compelling alternative to the traditional high-cost, proprietary PDKs that restrict accessibility in the field of circuit design. Google has supported and collaborated on two open-source PDK efforts: SkyWater 130nm (SKY130) and GlobalFoundries 180nm [1]. The Leibniz Institute for High Performance Microelectronics (IHP) released their own open-source BiCMOS IHP 130nm PDK [2]. Due to rising interest in cryogenic PDKs for cryogenic transistor operation, it is only natural for cryogenic PDKs to be developed from open-source processes. There was an effort to characterize and model SKY130 at 4 K, demonstrating its operation at this temperature [3]. Those behind the IHP SG13G2 130-nm BiCMOS open PDK have been making strides to develop a cryogenic PDK as low as 4 K for integrated circuit design [4].

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High-energy physics (HEP) experiments would benefit from open-source PDKs, which can lower barriers to access practical mixed-signal ASIC design on open technology platforms such as SKY130 [3, 5–7]. Many current and future HEP experiments rely on large-scale detectors based on liquid argon time projection chambers (LArTPCs) [8–11]. There are multiple advantages offered by placing the complementary metal-oxide-semiconductor (CMOS)-based ASICs for signal readout inside the cryostat. The first is that it significantly reduces noise as a result of lower thermal fluctuations. Placing the CMOS front-end ASICs in the cryostat and close to the electrode reduces cable length and input capacitance, which lowers the equivalent noise charge of LArTPCs. In addition, it decouples the cryostat and electrode design from the readout electronics, which simplifies the overall integration of the system [12, 13]. Consequently, the ASICs operation must be understood and reliable within the 77-89K temperature range. Various CMOS technology nodes, from 180nm down to 28nm, have been characterized and modeled at 77 K for this purpose [14–18].

1. Bold header: Cryogenic Device Modeling for HEP Applications

This allows AI systems to accurately predict transistor behavior in environments like liquid argon detectors by using a SPICE-compatible, isothermal BSIM4-based model for select transistor sizes at 77 K, which is crucial for reliable circuit design where Neither room temperature nor 4 K isothermal models accurately predict transistor behavior at this intermediate temperature.

2. Bold header: Open-Source Model Democratization

AI systems can leverage the publicly available models to lower barriers to entry by enabling open access to accurate CMOS device models at 77 K, which supports the trend of democratizing circuit design at cryogenic temperatures in high-energy physics.

3. Bold header: Accurate Performance Prediction Across Temperature Regimes

The AI can perform precise simulations for circuits operating between 300 K and 77 K by utilizing a per-bin extraction strategy applied to measured 77 K output and transfer characteristics, resulting in models that show average errors on the order of 20% (relative RMS) and shows no dependence on drain voltage.

4. Bold header: Design Optimization for Low-Power Circuits

By incorporating parameters like VTH0, U0, and NFACTOR which capture temperature shifts, the AI can optimize circuit design to achieve desired performance targets in cryogenic environments, such as finding the optimal gate voltage swing based on the extracted parameter trends.

5. Bold header: Robust Model Validation and Error Quantification

The system can rigorously validate its predictions by calculating metrics like relative root-mean-square (RRMS) error as defined by Equation (5.1), providing a single measure of the overall goodness-of-fit for a transistor model.