QuPort: Topology-, Port-, and Congestion-Aware Compilation for Modular Multi-QPU Quantum Systems

arXiv:2605.12583 · quant-ph, cs.MS · Submitted 2026-05-12 · Read on arXiv

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Introduction to the show: ident: Quantum Radio. Generated commentary on the latest quantum physics and condensed matter papers.

Kai: We're looking at the paper: "QuPort: Topology-, Port-, and Congestion-Aware Compilation for Modular Multi-QPU Quantum Systems".

Mira: Here's the gist of the paper. The gist The main partitioning method, TPCCAP, optimizes the implemented objective formed by weighted cut distance, communication-port overflow, and routed link-load congestion<ref:2605.12583#pg8> System Model Modular quantum processors require a compiler to reason about two resources at the same time: local device connectivity and communication across QPUs The framework studies this setting through an explicit three-level model: a weighted logical interaction graph, a directed physical coupling map, and an undirected QPU-level interconnect graph The input circuit after basis translation is denoted as C = (QL, G), where QL is the logical-qubit set and G is the ordered gate list For every two-qubit instruction on logical qubits i and j, the canonical edge weight is incremented: wij ← wij + 1, i < j.

Kai: Thus Wij = X t∈Tij γ t, where Tij is the set of two-qubit interaction times for the pair (i, j).> The modular target has N QPUs.

Mira: In the implemented configuration, each QPU has C compute qubits and P communication qubits A logical-to-QPU partition is a map π: QL → VQ Partitioning Objective The implemented TPCCAP objective is defined by Equation (14), which captures three compiler-level sources of modular cost: weighted cut distance, communication-port pressure, and routed congestion Algorithms QuPort employs several heuristic algorithms for partitioning and optimization 1.

Kai: Heavy-edge clustering constructs capacity-bounded clusters before assigning them to QPUs This method sorts interaction edges by decreasing weight and merges components incident to an edge when the merged component size remains at most K = C + P 2.

Title and authors: Mira: Let's talk about the title and authors of QuPort: Topology-, Port-, and Congestion-Aware Compilation for Modular Multi-QPU Quantum Systems. It’s by Soumyadip Sarkar and Subhasree Bhattacharjee. The title basically tells you what the paper is doing: optimizing compilation based on topology, ports, and congestion in multi-QPU systems.

Kai: So it’s not just about putting qubits somewhere; it’s about considering the whole system—how they connect physically, how many ports they have available for communication, and making sure the links between them don't get overloaded. It addresses that core problem of scaling up modular quantum processors.

Lev: From an engineering standpoint, the title signals that this isn't just a theoretical exercise; it’s a compilation framework built on Qiskit and Python that aims to solve the real-world issue of mapping circuits onto hardware architectures where communication is scarce.

Mira: It moves away from thinking about just a single coupling graph, which is what you do for one chip, and instead introduces that crucial QPU-level interconnect graph to capture the modular nature.

Kai: So it’s bridging the gap between the logical circuit and the physical reality of how those chips are actually wired up in a larger system.

Lev: It’s addressing that compiler problem where nonlocal gates become resources you have to assign, expose, and schedule instead of just treating them as simple nearest-neighbor operations.

Mira: That’s a big shift in thinking for distributed quantum computing research, moving the focus from just local routing to managing the entire communication budget across modules.

Kai: It sets up the stage for how we can study resource allocation before we get bogged down in choosing a specific physical interconnect protocol, which is exactly what you need right now.

Lev: It’s about making sure that when you design your program, you are proactively minimizing bottlenecks like communication-port overflow and routed link-load congestion.

The paper's summary: Kai: So the paper summarizes its approach by saying it uses an explicit three-level model: the weighted logical interaction graph, the directed physical coupling map, and the undirected QPU-level interconnect graph. This is how they see the problem mathematically.

Mira: They then explain that this model allows them to define a partitioning objective, which is that TPCCAP objective we talked about earlier. It captures three specific compiler-level costs: weighted cut distance, communication-port pressure, and routed congestion.

Lev: The summary points out that the implementation uses several heuristic algorithms to get there, starting with heavy-edge clustering to create capacity-bounded clusters before assigning them to QPUs.

Kai: Then they have balanced greedy partitioning which assigns logical qubits one at a time based on their weighted degree, and after that, they do local move refinement.

Mira: The TPCCAP local search starts from that balanced greedy partition and optimizes the objective function defined in Equation (fourteen) <ref:2605.12583#pg3>. It involves constructing a small candidate set of destination QPUs based on affinity to neighbors plus the current QPU.

Lev: Then there’s TPCCAP-SA, which adds a simulated annealing stage after TPCCAP to search for better partitions by accepting moves with probability exp minus delta T if the objective difference is negative.

Kai: So, in short, they’re taking a circuit and an architecture description and using these tools to find the best way to partition those logical qubits across QPUs while minimizing those three specific costs.

Mira: It’s a concrete methodology for partitioning that explicitly incorporates the constraints of the hardware structure into the optimization goal itself.

Lev: It shows how you can use this framework to generate a distributed program D(C) that separates local circuits from remote operations, which is key for distributed mode compilation.

The paper's improvements: Kai: Now, when we look at the suggested improvements, they focus on making the process more practical and adaptable. They suggest using QuPort to optimize qubit placement across multiple QPUs to minimize communication-port overflow and routed link-load congestion during large-scale distributed quantum neural network simulations.

Mira: That’s an application focused improvement—using this framework for training large quantum neural networks where you have many qubits spread out, and the goal is to keep the traffic manageable.

Lev: Another point they highlight is the distributed circuit representation D(C), which decouples local circuits C q from remote operations R, making it easier for AI systems to generate structured intermediate representations for hybrid quantum-classical algorithms.

Kai: It’s about giving an AI a clean way to separate what happens locally on one device versus what needs to happen across the network, which simplifies the overall program structure.

Mira: They also touch on topology-aware scheduling using a model that estimates makespan and peak link utilization based on circuit layers, allowing an AI to schedule remote operations greedily into rounds that respect port limits and shortest path link capacities.

Lev: And they have this adaptive remote operation modeling, where the cost for a remote operation is defined as tau remote(a, b) = d(a, b) tau E + tau eff C + tau R, which lets an AI scheduler dynamically weigh entanglement generation against classical communication costs.

Kai: So these improvements suggest using the framework not just for finding a static partition, but for dynamic scheduling and modeling the trade-offs of remote operations in a distributed setting.

Conclusion: Mira: To wrap up with QuPort, it provides a concrete framework for modular quantum compilation where logical placement, communication-port assignment, interconnect topology, congestion, remote-event extraction, and local-only routing are all represented explicitly. It’s a comprehensive system for handling the complexity of scaling up these systems.

Kai: The central contribution here is not about implementing a specific remote gate on superconducting hardware; it’s this compiler abstraction that keeps local routing separate from the QPU-level communication, which makes it suitable for studying the algorithmic structure before committing to a physical protocol.

Lev: From an error correction side, this framework shows how you can proactively manage resource pressure and congestion by using methods like TPCCAP and TPCCAP-SA to find partitions that respect capacity constraints.

Mira: It’s about providing a structured way to study the algorithmic structure of modular compilation under abstract latency assumptions, which is very valuable for theoretical work on scaling.

Kai: We’ve seen how this framework handles the core challenges of mapping circuits onto modular hardware by optimizing those three key costs: weighted cut distance, port pressure, and link load congestion.

Lev: And it gives us a way to generate structured distributed representations that are useful for both compilation and for AI systems trying to schedule operations across modules.

Mira: It’s a solid foundation for anyone working on the next generation of modular quantum hardware by giving them the tools to reason about these complex interactions before they start building specific physical interconnects.

Department of Computer Application, Narula Institute of Technology

quant-ph, cs.MS

Submitted: 2026-05-12

Updated: 2026-05-12

Journal ref: Sarkar, S., Bhattacharjee, S. Quport: topology-, port-, and congestion-aware compilation for modular multi-QPU quantum systems. Eur. Phys. J. Plus 141, 1206 (2026)

DOI: 10.1140/epjp/s13360-026-08358-1

Code: https://github.com/neuralsorcerer/quport

License: http://creativecommons.org/licenses/by/4.0/

Importance score: 73/100

The gist: The gist The main partitioning method, TPCCAP, optimizes the implemented objective formed by weighted cut distance, communication-port overflow, and routed link-load congestion<ref:2605.12583#pg8>

Key concepts

Weighted Logical Interaction Graph: This graph represents how logical qubits interact within the quantum circuit. Edges between qubits are weighted based on the frequency or importance of their two-qubit interactions, helping the compiler understand which qubit pairs need to communicate most frequently.
TPCCAP Objective: This is a cost function used to evaluate different ways of assigning logical qubits to physical QPUs. It combines three main costs: weighted cut distance (how far interactions are spread), communication-port pressure (if too many operations try to use the same communication port), and routed congestion (traffic on the links between QPUs).
Distributed Program Construction: This method transforms a single circuit into a distributed program D(C) by explicitly separating local circuits (operations within one QPU) from remote operations (gates that must happen across different QPUs). This structure is crucial for managing communication in modular systems.
TPCCAP Local Search: This is an optimization technique used after an initial partition to refine the assignment of logical qubits to QPUs. It iteratively tries small changes, considering the affinity of a qubit's neighbors and its current QPU, aiming to lower the overall cost function defined by TPCCAP.

Terminology

Abstraction — 1× in this paper · explained in 1 episode
Clustering — 1× in this paper · explained in 2 episodes

Summary

The gist The main partitioning method, TPCCAP, optimizes the implemented objective formed by weighted cut distance, communication-port overflow, and routed link-load congestion<ref:2605.12583#pg8>

System Model

Modular quantum processors require a compiler to reason about two resources at the same time: local device connectivity and communication across QPUs The framework studies this setting through an explicit three-level model: a weighted logical interaction graph, a directed physical coupling map, and an undirected QPU-level interconnect graph The input circuit after basis translation is denoted as C = (QL, G), where QL is the logical-qubit set and G is the ordered gate list For every two-qubit instruction on logical qubits i and j, the canonical edge weight is incremented: wij ← wij + 1, i < j. Thus Wij = X t∈Tij γ t, where Tij is the set of two-qubit interaction times for the pair (i, j).> The modular target has N QPUs. In the implemented configuration, each QPU has C compute qubits and P communication qubits A logical-to-QPU partition is a map π: QL → VQ

Partitioning Objective

The implemented TPCCAP objective is defined by Equation (14), which captures three compiler-level sources of modular cost: weighted cut distance, communication-port pressure, and routed congestion

Algorithms

QuPort employs several heuristic algorithms for partitioning and optimization

Heavy-edge clustering constructs capacity-bounded clusters before assigning them to QPUs This method sorts interaction edges by decreasing weight and merges components incident to an edge when the merged component size remains at most K = C + P
Balanced greedy partitioning assigns logical qubits one at a time in descending weighted degree After the greedy assignment, the implementation performs local move refinement
TPCCAP local search starts from the balanced greedy partition and optimizes the objective in Eq. (14) This involves constructing a small candidate set of destination QPUs based on affinity to v’s neighbors, together with the current QPU
TPCCAP-SA adds a simulated-annealing stage after TPCCAP A candidate move from π to π′ has objective difference ∆ = J(π′) − J(π). (16) The move is always accepted when ∆ ≤ 0. Otherwise, it may be accepted with probability Paccept = exp − ∆ T, where T is the current temperature

Distributed Program Construction

In distributed mode, QuPort applies the partition-aware layout without allowing a global inter-QPU routing pass to hide remote interactions The resulting program is D(C) =

D(C) =

where Cq is the local circuit for QPU q, and R is the ordered list of remote operations

Scheduling and Abstract Cost Semantics

QuPort includes a topology-aware estimator for comparing compiler choices under fixed abstract parameters For remote operations, the model uses three abstract terms: entanglement generation cost τE, classical round-trip cost τC, and remote-operation overhead τR

Implementation Properties

The implementation is organized around the same conceptual separation used in the mathematical model<ref:128 Implementation Properties. The configuration module defines the modular architecture and latency parameters<ref:128 Implementation Properties. The architecture module builds local and inter-QPU coupling structures<ref:128 Implementation Properties. Several correctness conditions are enforced by validation<ref:129 Implementation Properties. Proposition 1 states that every partition returned by heavy-edge clustering, balanced greedy partitioning, TPCCAP, or TPCCAP-SA satisfies the per-QPU capacity constraint<ref:130 Implementation Properties.

Compiler Semantics and Limitations

The framework should be interpreted as a compiler framework for modularmapping studies under abstract latency assumptions<ref:131 Compiler Semantics and Limitations. It does not provide a calibrated backend for a trapped-ion, superconducting, photonic, or neutralatom platform<ref:131 Compiler Semantics and Limitations. The algorithms are heuristic<ref:132 Compiler Semantics and Limitations. Heavy-edge clustering, balanced greedy partitioning, TPCCAP, and TPCCAP-SA are designed to expose and reduce compiler-level resource pressure; they do not guarantee optimal graph partitions<ref:132 Compiler Semantics and Limitations. The schedule estimator is a layer-based greedy model; it is not a verified network-control scheduler<ref:132 Compiler Semantics and Limitations.

Conclusion

QuPort provides a concrete framework for modular quantum compilation in which logical placement, communication-port assignment, interconnect topology, congestion, remote-event extraction, and local-only routing are represented explicitly<ref:135 Conclusion. QuPort provides a concrete framework for modular quantum compilation in which logical placement, communication-port assignment, interconnect topology, congestion, remote-event extraction, and local-only routing are represented explicitly. Its central contribution is not a hardware-specific remote-gate implementation but a compiler abstraction that keeps local routing separate from QPU-level communication<ref:135 Conclusion. The distributed compilation path turns cross-QPU gates into ordered remote events while preserving local circuits for Qiskit routing<ref:135 Conclusion. This makes QuPort suitable for studying the algorithmic structure of modular compilation before committing to a specific physical interconnect protocol.

References

The references listed are: Caleffi et al. Distributed quantum computing: A survey, Cirac et al. Distributed quantum computation over noisy channels, Davarzani et al. A hierarchical approach for building distributed quantum systems, Ferrari et al. Compiler design for distributed quantum computing, Ferrari et al. A modular quantum compilation framework for distributed quantum computing, Karypis and Kumar. A fast and high quality multilevel scheme for partitioning irregular graphs, Li et al.

Improvements for AI systems

Modular quantum system mapping for AI training: The QuPort framework can be used to optimize logical qubit placement across multiple QPU modules to minimize communication-port overflow and routed link-load congestion during large-scale distributed quantum neural network simulations.
Distributed circuit representation for complex algorithms: By using the distributed program construction output D(C) which separates local circuits from remote events, AI systems can generate highly structured intermediate representations for hybrid quantum-classical algorithms where classical control flow and remote quantum operations are explicitly decoupled.
Topology-aware scheduling for resource allocation: The topology aware estimator allows an AI to predict makespan and peak link utilization based on circuit layers, enabling the system to schedule remote operations greedily into rounds that respect endpoint communication port limits and shortest path link capacities.
Heuristic optimization for qubit connectivity: The heavy-edge clustering and balanced greedy partitioning algorithms can be employed by an AI agent to perform initial logical-to-QPU assignments that maximize the weighted cut distance objective, ensuring high-weight logical interactions remain local when capacity allows.
Adaptive remote operation modeling: The cost model for remote operations, defined as τremote(a, b) = d(a, b)τE + τeff C + τR, can be integrated into an AI scheduler to dynamically assess the trade-off between entanglement generation and classical communication costs when mapping quantum kernels across physically distant processors.

Abstract

Modular quantum processors require a compiler to reason about two resources at the same time: local device connectivity and communication across QPUs. A mapping that is acceptable on a single coupling graph may be unsuitable for a modular machine if it creates excessive cross-QPU traffic, concentrates that traffic on a small number of interconnect links, or assigns many boundary qubits to a QPU with few communication ports. This paper presents QuPort, a Python and Qiskit-based compilation framework that studies this setting through an explicit three-level model: a weighted logical interaction graph, a directed physical coupling map, and an undirected QPU-level interconnect graph. The main partitioning method, TPCCAP, optimizes the implemented objective formed by weighted cut distance, communication-port overflow, and routed link-load congestion. The framework also includes heavy-edge clustering, balanced greedy partitioning, simulated-annealing refinement, communication-port-aware layout, extraction of remote two-qubit operations, local-only routing of per-QPU circuits, and topology-aware schedule estimation. The model is a compiler-level abstraction. It does not claim a calibrated hardware runtime or an implementation of a physical remote-gate protocol.