Highly integrated quantum key distribution transmitter enabled by silicon photonics

The gist The paper demonstrates a highly integrated standalone QKD transmitter that combines silicon photonics with embedded electronics, real-time protocol processing, authentication, and thermal management in a compact board-level platform.

System Overview

The proposed system is a highly integrated standalone QKD transmitter built around a silicon photonic encoding chip fabricated using a commercial SOI process<ref:2607.23413#pg2> The transmitter integrates all essential functionalities required for practical QKD operation within a unified board-level architecture<ref:2607.23413#pg3> The complete transmitter occupies only 167×56×21 mm cubed (∼ 0.2 dm 3), which is comparable in size to a half-height, half-width PCIe card and more than 30 times smaller than a conventional 1U rack-mounted implementation<ref:2607.23413#pg6> Paired with a conventional discrete-component receiver, the transmitter achieves secure key rates of 219.1 kbps over 51.3 km and 17.9 kbps over 101.8 km of standard single-mode fiber, demonstrating performance comparable to conventional discrete-component systems<ref:2607.23413#pg7> This work establishes system-level integration as the next stage in the evolution of integrated QKD transmitters<ref:2607.23413#pg8>.

Optical Design

The optical subsystem follows a hybrid integration strategy, where high-speed quantum-state preparation functions are monolithically integrated on a silicon photonic chip<ref:2607.23413#pg9> This chip integrates quantum signal attenuation, decoy-state modulation, and polarization-state encoding The input pulse is coupled into the chip through a grating coupler and passes through a threestage PIN-based VOA which precisely controls the mean photon number in the quantum regime The high-speed decoy-state modulation stage comprises two multimode interferometers (MMIs), two thermo-optic phase shifters (TOPS11/12), and a carrier-depletion modulator (CDM1) A power-balancing stage, consisting of another pair of MMIs followed by CDM2, adjusts the relative optical power between the two orthogonal polarization components Finally, high-speed polarization-state encoding is achieved using CDM3 together with a two-dimensional grating coupler Trojan-horse attack protection is implemented using three optical isolators, providing a total isolation exceeding 160 dB while maintaining a compact optical layout.

Electronics Design

The electronic subsystem adopts a highly integrated architecture centered on a programmable system-on-chip (SoC) The SoC integrates processor cores and programmable logic within a single SoC, significantly reducing board area, interconnection complexity, and power consumption while maintaining flexible real-time protocol execution and precise timing control Stable system timing is ensured by an on-board oscillator together with a phase-locked loop (PLL) A dedicated hardware true random number generator (TRNG, QuantumCTek QCTWNG) supplies high-speed random numbers directly to the SoC through a low-voltage differential signaling (LVDS) interface High-speed digital signals generated by the SoC are serialized and routed to the photonic chip driver circuitry, where MAX3942 10-Gbps modulator drivers together with a high-speed amplifier provide stable, low-jitter modulation Identity authentication and key protection are provided by a dedicated secure element connected via the SPI interface.

Protocol Processing and Performance

The proposed transmitter integrates a complete real-time QKD protocol-processing framework within the embedded SoC, including message authentication, basis sifting, error correction, error verification, and privacy amplification for the standard decoy-state BB84 protocol Message authentication is initialized using pre-injected secret keys securely stored in an on-board secure element Detection events received from the receiver are processed in real time by the embedded FPGA, followed by basis sifting and error correction using the Winnow algorithm and error verification using CRC-64 Privacy amplification based on Toeplitz hashing is performed to remove residual information potentially available to an eavesdropper, yielding the final information-theoretically secure key. Experimental results show secure key rates of 219.1 kbps and 17.9 kbps over 51.3 km and 101.8 km of standard single-mode fiber, respectively During a continuous 12-hour experiment over 51.3 km of standard single-mode fiber, the system maintained stable secure-key generation, with both the secure key rate and the quantum bit error rate (QBER) exhibiting only minor fluctuations throughout the measurement period.

Conclusion

The proposed architecture provides a practical pathway toward compact, scalable, and costeffective QKD transmitters for applications ranging from size- and weight-constrained platforms, such as UAVs and small satellites, to large-scale access networks The work demonstrates the feasibility of translating integrated photonic chips into deployable standalone QKD transmitter hardware. Future work will focus on further heterogeneous integration of photonic and electronic subsystems, receiver miniaturization, and higher levels of system integration. The proposed transmitter extends this trend by consolidating the complete QKD functionality into a compact standalone board-level platform.

Table 1 Comparison of representative integrated QKD transmitter implementations shows that this work's implementation is an SOI PIC Auth. + THP Int. Int. Board-level (PCIe-card scale) with a thermal transmitter form. The comparison highlights a clear evolution in integrated QKD transmitters, where most reported systems still rely on external hardware for protocol execution or system control and remain laboratory prototypes or rack-mounted instruments. By combining integrated photonics, embedded electronics, and real-time protocol processing within a unified system architecture, it reduces the transmitter volume by more than a factor of 30 compared to a conventional 1U rack-mounted implementation while maintaining practical QKD performance. The proposed architecture offers a promising route toward scalable manufacturing and practical deployment of integrated QKD systems leveraging mature commercial silicon photonic technology. By combining integrated photonics, embedded electronics, and real-time protocol processing within a unified system architecture, it reduces the transmitter volume by more than a factor of 30 compared to a conventional 1U rack-mounted implementation while maintaining practical QKD performance. The proposed architecture provides a practical pathway toward compact, scalable, and costeffective QKD transmitters for applications ranging from size- and weight-constrained platforms, such as UAVs and small satellites, to large-scale access networks. More broadly, the transition from rack-mounted systems to compact board-level transmitters follows the evolutionary path that enabled the widespread deployment of classical optical communication, and is expected to facilitate the broader deployment of quantum-secure communication infrastructure in the post-quantum era. The proposed architecture provides a practical pathway toward compact, scalable, and costeffective QKD transmitters for applications ranging from size- and weight-constrained platforms, such as UAVs and small satellites, to large-scale access networks where multiple transmitters can share a centralized receiver. The proposed architecture provides a practical pathway toward compact, scalable, and costeffective QKD transmitters for applications ranging from size- and weight-constrained platforms, such as UAVs and small satellites, to large-scale access networks where multiple transmitters can share a centralized receiver. The proposed architecture provides a practical pathway toward compact, scalable, and costeffective QKD transmitters for applications ranging from size- and weight-constrained platforms, such as UAVs and small satellites, to large-scale access networks where multiple transmitters can share a centralized receiver.

1. Photonic Integration for On-Chip QKD State Preparation: The system can perform quantum-state preparation monolithically on a silicon photonic chip, integrating quantum signal attenuation, decoy-state modulation, and polarization-state encoding to create a highly integrated optical subsystem.

2. Miniaturized Transmitter Platform: The improved AI system can be deployed in compact board-level platforms like PCIe cards or half-height modules, achieving a volume reduction of more than 30 times smaller than a conventional 1U rack-mounted implementation.

3. Real-Time Protocol Execution: The embedded system can perform the complete post-processing chain locally within the transmitter, including message authentication, basis sifting, error correction, error verification, and privacy amplification for the standard decoy-state BB84 protocol.

4. Autonomous Key Management: The system can ensure continuous security by initializing message authentication using pre-injected secret keys securely stored in on-board secure element and automatically replacing consumed keys when the pool falls below a threshold.

5. System Stability and Robustness: The integrated hardware provides long-term operational stability, as demonstrated by maintaining stable secure key generation with minor fluctuations during a continuous 12-hour experiment over 51.3 km of standard single-mode fiber.