Fault-Tolerant Logical Operations and Efficient State Preparation in Modular Quantum Architectures with Noisy Interfaces

The gist The results show that interfaces can tolerate noise up to an order of magnitude higher than intra-QPU noise, with only a minor reduction in the fault-tolerance threshold

Distributed Fault-Tolerant CNOT Gate

The paper investigates the performance of fault-tolerant logical operations between distinct QPUs at the circuit level using lattice surgery in rotated surface code architectures. The logical CNOT is implemented by performing stabilizer measurements that cross the inter-QPU boundary, which requires a nonlocal implementation via gate teleportation using noisy Bell pairs. This nonlocal implementation introduces additional errors from Bell-pair imperfections and from the extra gates involved in the gate-teleportation protocol. The resulting error probability for a nonlocal two-qubit gate is assigned as αp = α · ϵ, where α is the interface noise parameter that captures additional noise associated with Bell-pair generation and gate-teleportation. Simulations comparing distributed configurations to monolithic ones show that the gap between the distributed and monolithic thresholds ranges from 2·10−3 to 3·10−3, indicating that the threshold behavior is dominated by local gate noise.

Distributed Fault-Tolerant GHZ State

The nonlocal CNOT construction serves as a fundamental primitive for generating fault-tolerant multipartite entanglement, specifically a distributed logical GHZ state. The preparation protocol involves preparing local logical GHZ states on each QPU and then iteratively merging them across the network using nonlocal logical CNOT gates. To prepare this state, the cost is determined by resource allocation, including ancilla patches and inter-QPU entanglement consumption. Ancilla minimization in this setting is equivalent to a vertex-cover problem on an associated graph, and a polynomial-time heuristic algorithm for finding low-overhead solutions was developed. The optimal ancilla count on a fixed merge tree is given by the minimum vertex cover number of the spanning tree, denoted as a(T) = τ(T).

Resource Trade-offs and Optimization

The paper characterizes the resource trade-offs in terms of ancilla overhead, state-preparation time, and nonlocal Bell-pair consumption for distributed GHZ state preparation. The number of physical Bell pairs consumed for a fusion operation between distance-d rotated surface code patches is d(2d − 1). A trade-off exists between ancilla economy and fusion time, where a star network minimizes the ancilla requirement but increases the state-preparation depth to O(n) compared to O(log n) for a linear network. A more relaxed requirement allows for parallel fusions, leading to a round count of DG = ∆(T), where ∆(T) is the maximum degree of the spanning tree.

Ancilla Minimization Heuristic

The problem of minimizing ancilla allocation is reduced to finding a spanning tree with a small vertex-cover number. Since exact vertex cover on general graphs is NP-hard, a heuristic approach called Star-Search was introduced to find low-cost solutions. This algorithm constructs a spanning tree by iteratively selecting high-degree center vertices to maximize the number of dominated nodes while reducing the required ancilla resources. The numerical comparison shows that BFS and DFS trees require, on average, the largest number of ancillas, whereas Algorithm 2 consistently outperforms both by producing spanning trees with smaller ancilla requirements.

Conclusion

The work provides quantitative guidance for the design of fault-tolerant modular architectures by showing that inter-QPU operations can tolerate noise levels up to an order of magnitude larger than those within individual QPUs. The findings offer a direct assessment of the reliability of distributed fault-tolerant logical entangling operations across QPU networks. Furthermore, the development of an efficient protocol for preparing distributed fault-tolerant logical GHZ states, characterized by resource trade-offs, offers quantitative guidance for designing modular quantum computing architectures. The framework suggests that extending this work to non-Clifford operations and communication-aware compilation will be important for assessing complete modular quantum-computing architectures.

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Fault-Tolerant Logical Operations and Efficient State Preparation in Modular Quantum Architectures with Noisy Interfaces

Siddardha Chelluri,1 Riccardo Mengoni,1 Tom Darras,1 Julien Laurat,2 Eleni Diamanti,3 and Ioannis Lavdas1, ∗

Welinq, 14 rue Jean Mac´e, 75011 Paris, France

Laboratoire Kastler Brossel, Sorbonne Universit´e, CNRS, ENS-Universite PSL, Coll̀ege de France, 4 Place Jussieu, 75005 Paris, France

LIP6, Sorbonne Universit´e, CNRS, 4 Place Jussieu, 75005 Paris, France

Modular quantum computing is a leading paradigm for scaling quantum computation beyond the resource limitations of monolithic devices In this architecture, multiple quantum processing units (QPUs), employing identical or distinct qubit modalities, are interconnected via shared entanglement. Here, we investigate how errors at module interfaces and within individual QPUs affect fault-tolerant computation when qubits are encoded using the rotated surface code. Going beyond the logical-memory benchmark, we perform circuit-level simulations of fault-tolerant nonlocal CNOT gates implemented via lattice surgery between QPUs connected by noisy Bell pairs, and analyze the resulting logical error rates. Our results show that interfaces can tolerate noise up to an order of magnitude higher than intra-QPU noise, with only a minor reduction in the fault-tolerance threshold. We further develop an efficient protocol for preparing distributed fault-tolerant logical GHZ states, reducing ancilla overhead, time, and nonlocal Bell-pair consumption. We show that ancilla minimization in this setting is equivalent to a vertex-cover problem on an associated graph, and introduce a polynomial-time heuristic algorithm for finding low-overhead solutions. Our results provide quantitative evidence that distributed quantum error correction can enable scalable, fault-tolerant quantum computation in modular architectures.

Introduction.— Distributed quantum computing offers a scalable route beyond monolithic devices by distributing algorithms across multiple quantum processing units (QPUs) interconnected via entanglement and classical communication [1–3] In such architectures, nonlocal quantum operations constitute the fundamental primitive for distributed quantum computation, enabling interactions between qubits hosted on different QPUs. Nonlocal operations are typically realized using shared entanglement together with teleportation-based protocols, making Bell-pair generation rates, classical communication rounds, and communication latency key resources [11]. These resource requirements have motivated extensive research on distributed circuit compilation and partitioning, including hypergraph-based methods and gate-reordering techniques that minimize the overhead associated with inter-QPU communication [12]. However, such approaches are generally studied at the level of unencoded circuits and do not directly address the additional overheads introduced by logical encoding and quantum error correction. Consequently, protocols that are efficient at the unencoded-circuit level need not remain efficient when implemented fault-tolerantly using logical qubits. Moreover, previous studies of distributed quantum error correction have largely focused on logical-memory benchmarks, which characterize the ability to preserve encoded quantum information under repeated error correction rounds, rather than on threshold analyses based on the implementation of fault-tolerant logical operations between QPUs. Understanding the performance of such operations is essential for assessing the viability of scalable distributed quantum computation. Since no quantum error-correcting code admits a universal set of transversal gates, scalable fault-tolerant quantum computation must rely on alternative constructions for logical operations. Lattice surgery [18–21] has emerged as one of the most powerful approaches, enabling logical entangling gates through sequences of stabilizer measurements rather than direct transversal implementations. Although lattice surgery is now well established for monolithic surface-code processors [18, 23], its extension to distributed architectures connected by noisy inter-QPU links remains largely unexplored.

In distributed implementations, the cost of a logical operation is determined not only by the underlying error-correcting code but also by the allocation of logical and ancilla patches across QPUs and by the scheduling of lattice surgery operations. Additional ancilla patches increase the physical-qubit footprint within each module, whereas longer operation sequences increase execution time and exposure to memory errors. Consequently, distributed lattice surgery naturally gives rise to a resource allocation problem in which different layouts can realize the same logical operation while exhibiting different trade-offs between spatial overhead and temporal cost.

Modular quantum computing is a leading paradigm for scaling quantum computation beyond the resource limitations of monolithic devices. In this architecture, multiple quantum processing units (QPUs), employing identical or distinct qubit modalities, are interconnected via shared entanglement. Here, we investigate how errors at module interfaces and within individual QPUs affect fault-tolerant computation when qubits are encoded using the rotated surface code. Going beyond the logical-memory benchmark, we perform circuit-level simulations of fault-tolerant nonlocal CNOT gates implemented via lattice surgery between QPUs connected by noisy Bell pairs, and analyze the resulting logical error rates.

1. Distributed Logical Entangling Operations for Fault-Tolerant Circuits: The improved system can perform circuit-level simulations of fault-tolerant nonlocal CNOT gates implemented via lattice surgery between QPUs connected by noisy Bell pairs, analyzing resulting logical error rates.

2. Efficient Preparation of Distributed Logical GHZ States: The system can implement a protocol for preparing distributed fault-tolerant logical GHZ states that reduces ancilla overhead, time, and nonlocal Bell-pair consumption by formulating ancilla minimization as a vertex-cover problem and using the Star-Search heuristic.

3. Scalable Modular Architecture Design: The system can guide the design of fault-tolerant modular quantum architectures by identifying trade-offs between spatial overhead (ancilla allocation) and temporal cost (state preparation time) based on graph theory analysis of QPU networks.