Stitched surface codes: planar concatenation through GHZ corridors

arXiv:2610.21357 · quant-ph · Submitted 2026-10-15 · Read on arXiv

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Introduction to the show: ident: Quantum Radio. Generated commentary on the latest quantum physics and condensed matter papers.

Kai: Today's paper: "Stitched surface codes".

Mira: The gist: This work presents a fault-tolerant quantum-memory architecture that concatenates four distance-t rotated surface-code patches with the

[4, 2, [Kai: First, who's behind it and why it matters.

Paper summary: Kai: So we've been talking about this paper, "Stitched surface codes: planar concatenation through GHZ corridors." It basically says they stitched together four rotated surface-code patches using a

[four two two: ] outer code.

Mira: And that stitching uses these GHZ corridors to measure the outer stabilizers without needing lattice surgery or long-range gates.

Lev: That's what I'm most interested in—how they manage that corridor overhead. It sounds like it scales linearly with the distance t, which is better than some other methods we've seen for connecting things up.

Kai: Yeah, and the whole point of this is to show a concrete way to build larger codes that still fit onto a square lattice without those huge gaps or complex routing.

Mira: It really shows that you can keep the structure planar, which is pretty neat because it keeps everything organized in one spot.

Lev: But we have to remember the tradeoff they mentioned—that this gain in qubits per logical qubit only really kicks in when the physical error rate drops below a certain point.

Kai: Right, so it's a testbed for architectures that are bigger than just one surface code patch, but still something you can build with current superconducting hardware.

Mira: It suggests that we don't always have to jump straight to the absolute biggest codes; sometimes this structured concatenation is the practical way forward.

Lev: It opens up new ideas for how we might arrange qubits on a chip when we want higher code distances than what a single patch can handle alone.

Conclusion: Kai: So, to wrap up this discussion on "Stitched surface codes: planar concatenation through GHZ corridors," we've been talking about how they built this system by stitching together four rotated surface-code patches with a

[four two two: ] outer code.

Mira: The title itself points to the core of the method: using those GHZ corridors as the communication backbone for measuring the outer stabilizers. It suggests a very specific, structured way to handle connectivity in these larger quantum systems.

Lev: And when we look at who wrote this, you have folks like them who are focused on building things that actually work on current hardware. They're showing how you can do this without needing surgery or those long-range gates that usually plague connecting distant parts of a surface code.

Kai: So the main implication here is practical: they've shown a way to embed these larger codes onto a square lattice in a planar layout, which is pretty neat because it keeps everything organized and avoids those huge gaps.

Mira: It really shows you can achieve distance two t protection by encoding two logical qubits, which is a significant step up from just one logical qubit.

Lev: But we have to remember that this gain in efficiency only really kicks in when the physical error rate drops below a certain point, so it's not just a magic fix for every noise level yet.

Kai: So what this means for us right now is that we have a concrete architecture that works on present superconducting devices, and the error scaling looks solid for the distance protection they're claiming.

Mira: The authors are demonstrating that this stitching method provides a near-term testbed for concatenated architectures beyond just the standard surface code.

Lev: It’s about showing how to arrange qubits in a way that makes sense for building bigger and better error correction structures on a chip today.

Kai: Now, we've seen the mechanics of how they build it, but what does this mean for actually trying to run these things at scale?

Mohamed A. Shalby, Alexandre Bourassa, Amir Karamlou, Leigh Martin, Alexis Morvan, Nicholas Noll, Craig Gidney, Leonid Pryadko

Google Quantum AI · University of California, Riverside

quant-ph

Submitted: 2026-10-15

Updated: 2026-10-15

Comments: 18 pages, 16 figures, 4 tables

License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/

Importance score: 83/100

The gist: The gist: This work presents a fault-tolerant quantum-memory architecture that concatenates four distance-t rotated surface-code patches with the [[4, 2, 2]] outer code to encode two logical qubits

Key concepts

Surface Code Patches: These are the fundamental building blocks of topological quantum error correction, arranged on a square lattice. They are used to encode local information and protect it against local errors. The paper uses four such patches, rotated at different angles, to create a larger logical code structure.
GHZ Corridors: These are narrow channels of ancillary qubits placed between adjacent surface-code patches. They serve as a dedicated path for measuring the outer-code stabilizer generators (XXXX and ZZZZ) using verified GHZ resource states. They allow for syndrome extraction across patch boundaries without needing physical connections or long-range gates.
Minimum Weight Perfect Matching (MWPM): This is the decoding algorithm used to interpret the error syndromes from the system. The paper specifically designed the corridor checks so that any fault mechanism, even those involving hyperedges in the corridors, decomposes into components that MWPM can handle by flipping at most two detectors.
Concatenated Architecture: This refers to combining smaller quantum error-correcting codes (the inner surface patches) with a larger outer code (the [[4, 2, 2]] structure). This nesting allows the system to achieve a higher overall code distance and better fault tolerance than using just one patch alone.

Summary

The gist: This work presents a fault-tolerant quantum-memory architecture that concatenates four distance-t rotated surface-code patches with the [[4, 2, 2]] outer code to encode two logical qubits at code distance d = 2t in a physical footprint of N 2 qubits on a square lattice with nearest-neighbor connectivity.

Architecture and Construction

The proposed architecture concatenates four distance-t rotated surface-code patches with the [[4, 2, 2]] outer code, obtaining a [[4t2, 2, 2t]] code of distance d = 2t that encodes k = 2 logical qubits in a footprint of N = 2d2 + 4d − 3 physical qubits on a square lattice with nn connectivity The two outer-code stabilizer generators GX = XXXX and GZ = ZZZZ, each of weight 4t, are measured sequentially by verified GHZ resource states prepared on narrow corridors of ancillary qubits between adjacent patches The corridors thread between patches using only nearest-neighbor gates and are operated alongside the standard surface-code stabilizer cycles, so the inner patches’ bulk stabilizer groups remain intact throughout outer-code extraction The corridor overhead, 8t+1 qubits, grows only linearly with the patch distance t

GHZ Corridor Preparation and Verification

The GHZ corridors introduce a potential structural complication for decoding because a single circuit-level fault inside the corridor can simultaneously trigger detectors in the corridor itself and in two or more adjacent patches, producing hyperedge fault mechanisms in the detector error model Decoders that natively handle hyperedges—e.g., belief propagation with ordered statistics (BP+OSD) [33, 34] and search-based decoders such as Tesseract [35]—can handle these mechanisms more accurately than minimum-weight perfect matching (MWPM), but at substantially greater runtime, which limits their use at scale and at real-time hardware cycle times Here we construct the corridor checks and verifiers to ensure that every such mechanism decomposes into graphlike components, so that the complete syndrome is decoded by a single MWPM pass A single GHZ preparation round (Fig. 2) constructs the resource state GHZ4t⟩ on the 4t corridor qubits using mid-circuit measurements [46] The protocol prepares clusters of corridor qubits in smaller GHZ states, measures intermediate qubits in the appropriate fusion bases to form a GHZ line, and absorbs the resulting Pauli corrections virtually as detector-frame updates

Decoding Mechanism

The decoder operates on the circuit-level detector error model (DEM) extracted by Stim [32] and uses minimumweight perfect matching (MWPM) [2, 36], which requires every fault mechanism to flip at most two detectors or to decompose into components that do The GHZ corridors add fault mechanisms that flip more than two detectors The corridor checks and verifier detectors are declared such that Stim decomposes every such mechanism into components that each flip at most two detectors The resulting DEM is decoded by a single PyMatching call over all four patches [36, 48] The outer-code detectors are nodes of the same matching graph, so error chains that cross patch boundaries are matched through them, and no separate outer-code decoding step is needed

Performance and Scaling

Circuit-level simulations show logical error rates that scale as ∼ pt, consistent with distance-2t protection The construction experimentally on a 105-qubit Willow superconducting processor in both the ZZ and XX memory bases With the correlated-matching decoder, increasing the code distance from d = 4 to d = 6 reduces the block logical error rate by a factor of 1.52 The asymptotic encoding density, k d2 N / Nsurf = 2(2t)2 / (8t2 + 8t − 3) for t→∞ is twice the single-patch ratio 1/2

Experimental Results and Tradeoffs

The hardware experiment on a 105-qubit Willow processor shows that the same architecture can be executed on a present superconducting device, with the logical error per cycle decreasing from d = 4 to d = 6 in both memory bases (Table II) The main practical tradeoff is the corridor prefactor: the asymptotic factor-of-two gain in qubits per logical qubit is realized below a crossover physical error rate that lies within reach of near-term superconducting hardware The stitched layout also packs both logical qubits into a single, nearly square region, whereas two independent patches of comparable distance form a rectangle

Conclusion

We have introduced a stitched concatenated memory that combines four rotated surface-code patches with the [[4, 2, 2]] outer detection code in a strictly planar nearest-neighbor layout The construction encodes two logical qubits at code distance d = 2t while using a physical footprint N = 2d2 + 4d − 3, and its verified GHZ corridors measure the two weight-4t outer stabilizer generators without lattice surgery, long-range gates, or workspace patches The construction provides a near-term testbed for concatenated architectures beyond the standard surface code

References

[1] A. G. Fowler, M. Mariantoni, J. M. Martinis, and A. N. Cleland, Surface codes: Towards practical large-scale quantum computation, Phys. Rev. A 86, 032324 (2012), arXiv:1208.0928

[2] E. Dennis, A. Kitaev, A. Landahl, and J. Preskill, Topological quantum memory, J. Math. Phys. 43, 4452 (2002), arXiv:quant-ph/0110143

[3] A. Y. Kitaev, Fault-tolerant quantum computation by anyons, Ann. Phys. 303, 2 (2003), arXiv:quantph/9707021

[4] C. Horsman, A. G. Fowler, S. Devitt, and R. Van Meter, Surface code quantum computing by lattice surgery, New J. Phys. 14, 123011 (2012), arXiv:1111.4022

[5] A. G. Fowler and C. Gidney, Low overhead quantum computation using lattice surgery, arXiv:1808.06709

[6] D. Litinski and F. von Oppen, Lattice surgery with a twist: Simplifying Clifford gates of surface codes, Quantum 2, 62 (2018), arXiv:1709.02318

[7] D. Litinski, A game of surface codes: Large-scale quantum computing with lattice surgery, Quantum 3, 128 (2019), arXiv:1808.02892

[8] Google Quantum AI, Suppressing quantum errors by scaling a surface code logical qubit, Nature 614, 676 (2023), arXiv:2207.06431

[9] Google Quantum AI and Collaborators, Quantum error correction below the surface code threshold, Nature 638, 920 (2025), arXiv:2408.13687

[10] S. Krinner, N. Lacroix, A. Remm, et al., Realizing repeated quantum error correction in a distance-three surface code, Nature 605, 669 (2022), arXiv:2112.03708

[11] Y. Zhao, Y. Ye, H.-L. Huang, et al., Realization of an error-correcting surface code with superconducting qubits, Phys. Rev. Lett. 129, 030501 (2022), arXiv:2112.13505

[14] I. Dumer, A. A. Kovalev, and L. P. Pryadko, Thresholds for correcting errors, erasures, and faulty syndrome measurements in degenerate quantum codes, Phys. Rev. Lett. 115, 050502 (2015), arXiv:1412.6172

[15] M. Freedman, D. Meyer, and F. Luo, Z2-systolic freedom and quantum codes, in Mathematics of Quantum Computation (Chapman and Hall/CRC, 2002)

[36] O. Higgott and C.

Improvements for AI systems

AI systems can achieve fault-tolerant quantum memory architectures by concatenating four distance-t rotated surface-code patches with a [[4, 2, 2]] outer code to encode two logical qubits at distance d = 2t. This provides a near-term testbed for concatenated architectures beyond the standard surface code.
AI systems can implement in situ measurement of outer-code stabilizer generators (XXXX and ZZZZ) by distributing verified Greenberger–Horne–Zeilinger (GHZ) ancillae through narrow corridors between patches, which requires without lattice surgery or long-range gates.
The decoding mechanism can be optimized by ensuring every such mechanism decomposes into graphlike components, so that the complete syndrome is decoded by a single minimum-weight-perfect-matching pass, even when hyperedge fault mechanisms are introduced.
AI systems can dynamically determine the optimal verification depth (rv) based on physical error rates (p) to minimize logical error rates, as the optimal rv depends on t and p.
AI systems can utilize correlated matching (Corr-MWPM) in decoding to achieve lower logical error probabilities, as it shows better accuracy than plain MWPM, reducing the block error probability by a factor of 1.52 when increasing distance from d = 4 to d = 6.
The architecture allows for the encoding of two logical qubits with an asymptotic encoding density of k/n = 1, which is twice the single-patch ratio.