Accurate gap control of 3D-integrated superconducting quantum circuits using asymmetric indium architecture and multi-angle flip-chip bonding

arXiv:2610.21435 · quant-ph · Submitted 2026-10-15 · Read on arXiv

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Introduction to the show: ident: Quantum Radio. Generated commentary on the latest quantum physics and condensed matter papers.

Kai: I'm Kai.

Mira: And I'm Mira, here with Lev.

Kai: Today's paper: "Accurate gap control of 3D-integrated superconducting quantum circuits using asymmetric indium architecture and multi-angle flip-chip bonding".

Mira: The gist: An asymmetric indium architecture combined with multi-angle compression establishes a robust,

Kai: First, who's behind it and why it matters.

Paper summary: Kai: So we're looking at this paper titled "Accurate gap control of three dee-integrated superconducting quantum circuits using asymmetric indium architecture and multi-angle flip-chip bonding" <ref:2610.21435#pg1,Accurate gap control of 3D-integrated superconducting quantum circuits using asymmetric indium>. It tackles how to get accurate spacing between chips when you stack them in a flip-chip way, which is really important for scaling up these quantum processors.

Mira: Exactly. The main idea they're pushing is that conventional methods with thick indium bumps on both sides aren't great because you end up with residual tilt, and this paper proposes a different setup to manage that.

Lev: So the core of their proposal seems to be splitting the fabrication flows: using twenty micrometer thick indium bumps on the control chip, while the qubit chip uses much thinner two hundred nanometer pads for its connections.

Kai: Right, so they're changing how they build those connections based on which chip it is.

Mira: That separation of fabrication makes sense because it tries to keep the qubit side cleaner for coherence by limiting thick indium evaporation there.

Lev: And then they introduce a multi-angle compression procedure after bonding to actively suppress that tilt, showing results where the average post-bonding tilt drops down to twenty plus twelve microradians.

Kai: That's a big reduction from what you might see without that extra step.

Mira: It shows they found a way to control the spacing better than just relying on static spacers and hoping for the best alignment.

Lev: They also mention that using this asymmetric indium architecture combined with multi-angle compression leads to low resistance and low loss interconnects, which is crucial for keeping your quantum information from getting lost during transport.

Kai: So it's not just about spacing; it's about making sure the wires themselves are good conductors too.

Mira: Right, because if you have high loss in the interconnects, all that good spacing control won't matter if the signal dies along the way.

Kai: And they put these results in terms of qubit performance, showing that transmon qubits integrated this way reach relaxation and coherence times of T1 equal to one hundred fifty-nine plus fourteen microseconds.

Paper summary: Mira: That's comparable to planar devices, which is a really strong point because it means the integration method isn't hurting the actual quantum properties as much as you might expect.

Lev: For us on the hardware side, that T1 time of one hundred fifty-nine plus fourteen microseconds compared to a planar reference of one hundred sixty-seven plus thirty-four microseconds tells us that this process is viable for building real hardware today.

Kai: So if we're looking at putting this into a larger system, we've got a route that doesn't immediately kill our coherence times.

Mira: I think what they’re really highlighting with the "Accurate gap control of three dee-integrated superconducting quantum circuits using asymmetric indium architecture and multi-angle flip-chip bonding" paper is how you can systematically tackle the mechanical challenges of stacking chips in a three dee stack <ref:2610.21435#pg1,Accurate gap control of 3D-integrated superconducting quantum circuits using asymmetric indium>.

Kai: It's about solving that precise spatial control issue without ruining the delicate quantum state.

Lev: The method they test involves comparing a single bonding process, where things just bond, against using spacers and then testing how many angles you need to compress the sample to get the tilt down to twenty plus twelve microradians.

Mira: So they are showing that the multi-angle compression is the key mechanism for mitigating those systematic tilting issues that plague flip-chip assembly.

Kai: The paper shows that their specific architecture, with twenty micrometer thick indium bumps on the control chip and two hundred nanometer thin pads on the qubit chip, works well electrically.

Mira: That's important because it directly links the physical structure of the bond to its performance in terms of resistance and loss.

Lev: They also quantified how this approach affects circuit parameters, noting that a larger spacing reduces capacitance and therefore increases charge energy and qubit frequency, but the Josephson energy is unaffected.

Kai: So they're showing a trade-off where you can tune some things by changing the physical gap while keeping others stable.

Mira: And they also point out that when they test with SU-eight spacers, the compression stress corresponds to a compression of approximately two hundred twenty-eight nanometers, which aligns with how much spacing they actually achieved.

Lev: That's good validation because it connects the macroscopic mechanical action to the microscopic results in a predictable way.

Paper summary: Kai: This whole work basically establishes this asymmetric indium bonding with multi-angle compression as a robust route for three dee integrated superconducting quantum processors <ref:2610.21435#pg1>.

Mira: It’s establishing a reliable path forward for moving beyond just planar designs into true three-dimensional integration for these kinds of circuits.

Lev: It gives us a concrete way to handle the gap control issue when we think about scaling up the number of qubits on a chip without introducing major systematic errors from the stacking process.

Kai: So it moves the conversation from "can we do it?" to "how do we do it reliably?"

Mira: It shows that by being smart about the architecture and applying compression, you can maintain coherence times that are competitive with what we see in planar devices.

Lev: Which means the overhead of this integration technique isn't too punishing on the actual quantum computation itself.

Kai: This paper is a really solid piece of work for anyone trying to design hardware for these systems because it gives us a blueprint for managing those complex inter-chip connections.

Mira: It’s not just about the physics of the qubits, but also the engineering reality of putting them on top of each other.

Lev: The limitation they point out is that they are focusing on specific chip dimensions, like fourteen point three by fourteen point three millimeters for their measurements, and they discuss how those effects might change when you move to much larger area assemblies.

Kai: So the real challenge ahead is taking this principle and making it work reliably across much bigger processor layouts where chip-scale deformations get more complex.

Mira: The paper does a good job of showing that even with these physical challenges, the circuit parameters, like qubit frequencies and charge energies, only show deviations at the few percent level before and after flip-chip assembly.

Lev: That level of deviation is what we need to worry about when designing error correction schemes for this kind of hardware.

Kai: So in short, this paper lays out an architecture—asymmetric indium bonding combined with multi-angle compression—that offers a way to get precise gap control while preserving qubit coherence.

Mira: It provides a foundation for building the next generation of scalable three dee integrated superconducting quantum processors <ref:2610.21435#pg1>.

Conclusion: Kai: So we're wrapping up this look at the paper "Accurate gap control of three dee-integrated superconducting quantum circuits using asymmetric indium architecture and multi-angle flip-chip bonding." Mira What's the actual takeaway here?

Lev: The authors are showing how you can fix the big problem in flip-chip stacking, which is that things tilt after bonding.

Kai: They use this specific setup with different indium thicknesses on each chip, control chip at twenty micrometers thick and qubit chip at two hundred nanometers thin.

Mira: That separation of fabrication flows seems like a smart way to keep the delicate qubit side from getting messed up by thick layers during processing.

Lev: And they combine that with this multi-angle compression procedure which actively reduces the tilt angle down to twenty plus twelve microradians.

Kai: So, when you look at the title, it’s really about achieving accurate gap control in these three dee integrated superconducting circuits through asymmetric indium architecture and multi-angle flip-chip bonding.

Mira: It seems like they’re proving that this combination isn't just a clever trick but a robust way to handle the mechanical challenges of stacking chips.

Lev: From what I see, it means we have a more reliable path toward building real hardware because the systematic errors from the assembly process are being managed.

Kai: For someone listening, it means that when we stack these quantum circuits up, we can trust that the spacing between them stays pretty consistent without having to fix huge alignment problems later.

Mira: It suggests that coherence times on these three dee integrated devices can actually be comparable to what we get from just planar devices.

Lev: That comparison is important because it tells us this technique doesn't introduce extra loss channels that would kill the quantum information we’re trying to protect.

Kai: So, this work establishes asymmetric indium bonding with multi-angle compression as a solid way forward for making larger three-dimensional integrated superconducting quantum processors.

Mira: It sets a foundation for scaling up these systems because it addresses the physical reality of how you connect these chips without destroying the quantum state.

Lev: We need to see if this control method scales well when we move beyond those specific chip sizes they used in their measurements, that's where the next step comes in.

L. Richard, N. Bruckmoser, J. Feigl, D. Bunch, A. Bhattacharjee, L. Koch, I. Tsitsilin, V. P Bader, H Hu, L Söodergren, Á Filipp

Technical University of Munich School of Natural Sciences Department of Physics Institute Walther-Meෳsner-Institut Bayerische Akademie der Wissenschaften Peak Quantum GmbH Munich Center for Quantum Science and Technology Munich Quantum Valley gGmbH

quant-ph

Submitted: 2026-10-15

Updated: 2026-10-16

Comments: 14 pages, 4 main figures, 5 appendix figures

License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/

Importance score: 87/100

The gist: The gist: An asymmetric indium architecture combined with multi-angle compression establishes a robust, coherence-preserving route toward 3D-integrated superconducting quantum processors Flip-Chip

Key concepts

Asymmetric Indium Architecture: This strategy uses different indium bump thicknesses on the two chips involved in flip-chip bonding. The control chip receives thick (20 µm) bumps, while the qubit chip receives very thin (200 nm) pads. This separation is designed to manage fabrication constraints and maintain high coherence by limiting thick indium deposition on the sensitive qubit side.
Multi-Angle Compression: This involves bonding the chips through four compression steps at successive 90-degree orientations. This procedure actively suppresses systematic tilt that occurs during assembly, reducing the average post-bonding tilt to (20±12) µrad. It ensures high parallelism and precise control over the inter-chip spacing.
Qubit Coherence ($T_1$ and $T_{2,echo}$): These metrics measure how long a superconducting qubit can maintain its quantum state without losing information (relaxation time $T_1$) or dephasing (echo time $T_{2,echo}$). The results show that qubits integrated using this method achieve T1 of (159±14) µs and T2 of (294±42) µs, which are comparable to standard planar devices, proving the technique preserves quantum performance.

Terminology

Quantum Circuits — 1× in this paper · explained in 2 episodes

Summary

The gist: An asymmetric indium architecture combined with multi-angle compression establishes a robust, coherence-preserving route toward 3D-integrated superconducting quantum processors

Flip-Chip Integration Strategy

Flip-chip 3D integration is an important approach for scaling circuits beyond planar architectures in superconducting quantum processors. This technology requires accurate and uniform control of the inter-chip spacing while preserving qubit coherence. Conventional processes use thick indium bumps on both chips, but this approach utilizes an asymmetric architecture where the control chip has 20 µm thick indium bumps and the qubit chip carries 200 nm thin indium pads. This separation of fabrication flows is designed to preserve high coherence on the qubit chip by restricting resist-based spacer fabrication and thick indium evaporation to the control chip.

Spacing Control via Multi-Angle Compression

A critical requirement for scalable three-dimensional superconducting quantum processors is accurate control of the inter-chip spacing after assembly. The study compares three strategies for investigating the influence of spacers and bonding procedures on spacing accuracy.

** Group (a) consists of samples bonded without spacers, using a single compression step. This group reaches the target spacing of 10 µm on average, but exhibits substantial spatial variation with a root-means-square (rms) spatial standard deviation of 511 nm. The polar tilt angle for this group is θa = (248 ± 118) µrad. This variation is primarily attributed to chip tilt, as reflected by the average polar angle of θa = (248 ± 118) µrad. The azimuthal angles for single-compression samples cluster around a preferred orientation of approximately π/2 rad. Group (b) incorporates SU-8 spacers with an average height of 10.28 ± 0.07 µm across a 4-inch wafer. This group shows an rms spatial standard deviation of 418 nm and a polar tilt angle of θb = (209 ± 84) µrad. Group (c) includes the same spacers and is bonded using a multi-angle compression sequence. This procedure involves four compression steps at successive 90◦ orientations, which reduces the polar tilt to θc = (20 ± 12) µrad. The multi-angle bonding procedure largely eliminates this systematic contribution, resulting in a mean spacing of 10.04 µm and an rms spatial standard deviation of 64 nm. This parallelism is preserved at processor-relevant chip dimensions of 14.3 × 14.3 mm2 with a residual tilt of (23 ± 8) µrad. The SU-8 spacers exhibit a compressive stress corresponding to a compression of approximately 228 nm, in agreement with the measured reduction in spacing. The inter-chip spacing is reconstructed by combining SEM measurements at the overlapping chip edges with profilometer scans of the exposed qubit-chip back side plane. The use of a quadratic surface assumes that the dominant chip-scale deformation consists of a combination of global tilt and bowing of the silicon chips. The polar tilt angle θ is obtained from the magnitude of the out-of-plane gradient, defined by θ = arctan q / (b2x + b2y). The azimuthal angle ϕ, defining the in-plane direction of the tilt, is given by ϕ = arctan 2(by, bx). The results demonstrate that the multi-angle procedure maintains high parallelism when extended to larger-area flip-chip assemblies. The residual offset between the final bonded spacing and the original spacer height is discussed in Appendix C. The mean chip-to-chip spacing is calculated as the average of z(x, y) over the bonded area. The spatial variation is quantified by the standard deviation of z(x, y) over the same area. The results demonstrate that the multi-angle procedure sufficiently mitigates the effects of residual tilt, rendering the possible benefit of an etched silicon window negligible in this regard. The individual circuit-parameter deviations are listed in Table A1. The qubit frequencies and charge energies exhibit similar behavior, with deviations at the few-percent level before and after flip-chip assembly. The comparison demonstrates that the flip-chip architecture with multi-angle bonding does not lead to unwanted deviations in circuit parameters. The individual relaxation and echo-dephasing times are listed in Table A2. The comparable coherence performance between flip-chip and planar devices demonstrates that the asymmetric indium integration process preserves transmon coherence. This establishes asymmetric indium bonding with multi-angle compression as a robust, coherence-preserving integration route. The interconnects formed by this process are both electrically robust and low-loss. Single transmons integrated with this process reach T1 = (159 ± 14) µs, comparable to the T1 = (167 ± 34) µs of planar reference qubits fabricated without flip-chip integration. The results establish asymmetric indium bonding with multi-angle compression as a robust, coherencepreserving integration route and a scalable foundation for large-scale three-dimensional integration of superconducting quantum processors. 3D integrated superconducting qubits are established as an important approach for scaling circuits beyond planar architectures in superconducting quantum processors. The main requirement to realize this technology is the reliable fabrication of superconducting chip-to-chip interconnects that provide both mechanical and galvanic contact. Thick indium layers, however, introduce additional fabrication constraints on the qubit chip that can affect device performance. Alternative indium interconnect geometries have been explored to overcome these limitations. A critical requirement for scalable three-dimensional superconducting quantum processors is accurate control of the inter-chip spacing after assembly. Rigid spacer structures, such as resist or silicon spacers, have been introduced to address this limitation by defining a minimal inter-chip separation. However, while spacers may establish a lower bound for the vacuum gap, they do not guarantee post-bonding parallelism. The control chip incorporates 20 µm thick indium bumps and resist-based spacers, while the qubit chip carries 200 nm thick indium pads that preserve adhesion and galvanic connection. Additionally, a multi-angle compression procedure suppresses residual tilt and enables precise control of the post-bonding inter-chip spacing. The flip-chip architecture affects the circuit parameters most notably through the readout-resonator frequencies and the qubit capacitance. A larger spacing reduces Cq and therefore increases Ec and fq, while EJ is unaffected. The flip-chip device exhibits an average relaxation time of T1,avg = (159 ± 14) µs across six qubits. The comparable coherence performance between flip-chip and planar devices demonstrates that the asymmetric indium integration process preserves transmon coherence and does not introduce significant additional loss channels within the sensitivity of the present measurements.

Improvements for AI systems

Bold Header: Improved 3D Integration Reliability

By employing an asymmetric indium architecture combined with multi-angle compression, AI systems can be engineered to achieve low-resistance and low-loss indium interconnects while ensuring that the average post-bonding tilt is reduced to (20 ± 12) µrad.

Bold Header: Enhanced Circuit Parameter Targeting

The improved system can maintain circuit performance by mitigating geometric errors, as the paper demonstrates that a residual tilt of approximately "20 µrad achieved with the multi-angle process corresponds to only 0.2 µm spacing deviation, reducing the potential absolute deviation in circuit parameter attributed to tilt below 0.2 % for the resonator and qubit frequencies."

Bold Header: Optimized Coherence Preservation

AI systems utilizing this architecture can be designed to preserve qubit coherence, as single transmons integrated with this process reach T1 = (159 ± 14) µs, comparable to the T1 = (167 ± 34) µs of planar reference qubits fabricated without flip-chip integration.

Bold Header: Low-Loss Microwave Routing

The system can incorporate microwave routing between chips using indium transitions, which are characterized by a loss tangent of "δIn < 1 × 10−7 per indium transition, indicating that the interconnects are both electrically robust and low-loss."