HAWC-Leak: Heterogeneous Architecture Workload Classification utilizing Side-Channel Leakage

The gist: HAWC-Leak presents a dynamic workload classification framework that identifies specific hardware accelerator tasks in real time using non-invasive power analysis and achieves 100% classification accuracy across all evaluated scenarios.

Motivation and Problem Statement

Modern computing systems are increasingly heterogeneous, integrating general-purpose CPUs with GPUs, FPGAs, and domain-specific AI accelerators to meet the escalating performance and energy-efficiency demands of emerging workloads. These platforms introduce critical security vulnerabilities where power consumption patterns can leak sensitive runtime information. Existing methods struggle to profile complex, dynamic systems where diverse workloads coexist on shared hardware resources. If an attacker can identify exactly when and how different computational workloads execute, they can infer proprietary algorithms or monitor user activity. A key challenge is the presence of heterogeneous execution noise arising from concurrent accelerator activity and system-level background processes. Existing detection methods often fail in these scenarios because they rely on simple thresholding or non-hierarchical classification that cannot distinguish between the sharp spectral signature of a cipher and the broad power envelope of an AI accelerator.

Experimental Setup and Data Collection

The research constructed a complete end-to-end measurement pipeline using the ChipWhisperer (CW) platform and a Xilinx Artix-7 FPGA platform. The setup emulated a realistic edge-computing scenario by deploying diverse IP cores, including AES-128, ECC P-256, SHA-256, and a Convolutional Neural Network (CNN). To test mixed conditions, the researchers generated controlled mixed-activity power traces where multiple accelerators are instantiated on the same fabric while only one executes at a time. The ChipWhisperer provides synchronous sampling, which significantly reduces timing jitter and enables precise capture of high-frequency transient signals. Power measurement was performed on the VCCINT rail using a shunt-resistor-based path to ensure direct observation of instantaneous current draw from the programmable logic fabric.

Data Composition and Preprocessing

The dataset construction involved preparing FPGA bit streams targeting the Xilinx Artix7 A100T device on the CW305 evaluation platform. These bitstreams included single-accelerator configurations (AES, ECC, SHA-256) and an idle configuration to capture baseline leakage. To simulate realistic deployment environments, a combined AES and ECC bitstream was used with a mode-selection register to control runtime switching between the two accelerators. For the CNN workload, 16 × 16 pixel inputs were processed through a custom Verilog core to generate traces driven by data-dependent switching activity. Raw power traces were subjected to zero-mean normalization to remove DC offset variations. A set of 21 statistical and spectral features was extracted, including Time-Domain Features like Mean, Standard Deviation, and Entropy, and Frequency-Domain Features such as the Power Spectrum Peak.

Hierarchical Classification Architecture

The framework employs a two-stage Random Forest classifier to effectively distinguish between shortduration operations and longer workloads.

1. Stage 1 is a Binary AES Detector utilizing a sliding window approach (window size = 129 samples, stride = 32) to detect AES vs. Rest. If any window yields an AES probability exceeding a threshold (τ > 0.45), the entire trace is classified as AES.

2. Stage 2 is a Multi-Class Classifier that receives traces where Stage 1 was negative, discriminating between ECC, Idle, SHA-256, and CNN using features extracted from the full trace duration.

Key Findings and Analysis

The proposed hybrid hierarchical model achieved a global accuracy of 100% across all test scenarios. The feature importance analysis revealed distinct hierarchies for the two stages. For Stage 1, Spectral Rolloff and Spectral Centroid were the most dominant features, suggesting high-frequency switching characteristics are key to distinguishing AES from other workloads. For Stage 2, time-domain metrics like Peak-to-Peak Ratio and Crest Factor gained significance for discriminating between ECC, SHA-256, and CNN based on amplitude profile. Principal Component Analysis (PCA) projection confirmed that the AES (blue) and ECC (red) clusters exhibit closer proximity in the feature space, physically justifying the need for a hierarchical architecture to resolve this ambiguity. The model maintained 100% accuracy on AES Mixed and ECC Mixed datasets, validating the efficacy of the sliding window approach in isolating AES signatures even when interleaved with other system activities. Future work plans include exploring unsupervised clustering methods like IIC-SCA to enhance robustness against overfitting to static training sets.

Conclusion

HAWC-Leak successfully demonstrated that distinct accelerator workloads exhibit identifiable power signatures even in the presence of background leakage from idle modules. The framework establishes a strong baseline for scalable workload fingerprinting using non-invasive power side-channel analysis. It confirms that power consumption acts as a highfidelity barcode for hardware execution, remaining readable even in the noisy environment of a modern heterogeneous architecture. The current framework supports only a single active workload at a time, but the results establish a strong baseline for scalable workload fingerprinting.

REFERENCES

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1. A dynamic workload classification system can be developed to identify specific hardware accelerator tasks in real time using non-invasive power analysis, as HAWC-Leak does by targeting the runtime behavior of heterogeneous systems, leveraging machine learning to predict the active workload from feature extracted power traces captured during execution.

2. The improved AI system can perform real-time inference on heterogeneous computing platforms by accurately identifying which specific accelerator is executing at any given moment in a mixed-activity scenario where multiple accelerators are instantiated.

3. The system will be capable of distinguishing between diverse workloads, including Advanced Encryption Standard (AES-128), Elliptic Curve Cryptography (ECC P-256), Secure Hash Algorithm (SHA-256), Convolutional Neural Network (CNN), and a system idle state, with 100% classification accuracy across all evaluated scenarios.

4. The framework can operate in complex, realistic deployment environments where overlapping static and dynamic power components obscure individual workload signatures, allowing for reliable profiling even when multiple accelerators are instantiated on the same fabric, while only one executes at a time.

5. The system will utilize a hierarchical Random Forest classifier with two stages: a binary AES detector using a sliding window to pinpoint short operations, followed by a multi-class classifier to discriminate between remaining classes like ECC, Idle, SHA-256, and CNN.

6. The feature extraction process will incorporate both time-domain metrics (Mean, Standard Deviation, Root Mean Square Error (RMSE), Energy) and frequency-domain features (Fast Fourier Transform (FFT) applied to extract the Power Spectrum Peak) to capture distinct switching characteristics for different hardware cores.

7. By leveraging Principal Component Analysis (PCA) on 21 extracted feature vectors, the system can map power signatures into a 2-dimensional latent space that reveals well-defined, compact clusters for classes like CNN and Idle, while resolving the ambiguity between AES and ECC which are physically closer in this projection.

8. The system's robustness will be enhanced by incorporating unsupervised learning methods like Invariant Information Clustering (IIC-SCA) to ensure adaptation to diverse operational profiles without relying on labeled ground truth, addressing the concern of potential overfitting to the specific noise profiles and experimental conditions.

Modern heterogeneous computing platforms, which integrate general-purpose processors with specialized accelerators such as FPGAs, have become the standard for high-performance and embedded applications. However, the shared physical resources of these systems introduce critical security vulnerabilities, where power consumption patterns can leak sensitive runtime information. While side-channel analysis is well established for extracting cryptographic keys from isolated algorithms, existing methods struggle to profile complex, dynamic systems where diverse workloads coexist on shared hardware resources. This paper presents HAWC-Leak, a dynamic workload classification framework designed to identify specific hardware accelerator tasks in real time using non-invasive power analysis. Unlike prior studies focused on extracting cryptographic secrets from isolated implementations, our approach profiles heterogeneous runtime behavior using machine learning to predict active workloads from features extracted from power traces. We implement a complete hardware-in-the-loop measurement testbed using the ChipWhisperer CW305 Artix-7 FPGA platform to capture high-resolution power signatures of diverse workloads including Advanced Encryption Standard (AES-128), Elliptic Curve Cryptography (ECC P-256), Secure Hash Algorithm (SHA-256), Convolutional Neural Network (CNN), and a system idle state. We develop a Hierarchical Random Forest classifier that processes real-time power data to identify the executing application in controlled mixed-activity scenarios where multiple accelerators are instantiated but only one executes at a time. Experimental results demonstrate that this framework achieves 100% classification accuracy across all evaluated scenarios, confirming that power consumption patterns serve as a reliable and distinctive fingerprint for profiling heterogeneous runtime behavior.