High-fidelity and robust controlled-Z gates for superconducting transmon qubits. II. System-parameter uncertainties and overall errors

arXiv:2610.30681 · quant-ph · Submitted 2026-10-22 · Read on arXiv

Listen

Transcript

Introduction to the show: ident: Quantum Radio. Generated commentary on the latest quantum physics and condensed matter papers.

Kai: We're looking at the paper: "High-fidelity and robust controlled-Z gates for superconducting transmon qubits. II. System-parameter uncertainties and overall errors".

Mira: Here's the gist of the paper. My analysis combines all relevant information to construct a comprehensive, detailed summary, ensuring no critical technical nuance is overlooked.

Kai: Here is the detailed summary: Comprehensive Summary of High-Fidelity and Robust Controlled-Z Gates Framework This work presents a unified and highly robust optimal control framework designed to engineer high-fidelity controlled-Z (CZ) gates in superconducting transmon qubits, specifically addressing the challenges posed by both stochastic noise and systematic parameter uncertainties.

Mira: The central goal is to develop gate operations that are intrinsically less sensitive to experimental fluctuations, thereby significantly reducing the need for exhaustive characterization and frequent recalibration, which is crucial for scaling up superconducting quantum processors.

Kai: Core Framework and Error Characterization The research establishes a unified framework by combining noise-robust control strategies developed in a preceding work (Part I) with novel parameter-robust control strategies developed in the current study (Part II).

Paper summary: Kai: So we're looking at this paper right now, "High-fidelity and robust controlled-Z gates for superconducting transmon qubits. II. System-parameter uncertainties and overall errors." It’s about taking the control framework they built in the first part—the one for suppressing noise—and extending it to handle when things aren't just noisy, but when your parameters are off.

Mira: Exactly, Kai. The main thesis here is that you can design gates that don't rely on knowing every single number perfectly beforehand. It’s about making the gate operations inherently less sensitive to those parameter uncertainties in coupling strength, anharmonicities, and qubit frequencies.

Lev: From my side, if we try to run these kinds of pulses on real hardware right now, we’re looking at a lot of overhead just trying to characterize all those parameters before we can even start the gate sequence.

Kai: Right, so they classify the uncertainties into two groups: perturbations to the off-diagonal coupling strengths and things that mess with the diagonal detunings of the Hamiltonian. And they claim there are different ways to suppress each type of error.

Mira: That’s a key distinction because it means you don't use one trick for everything; you need separate strategies for those two classes of parameter drift.

Lev: I wonder how much overhead that dynamical decoupling causes, especially when we have to modulate the detuning to suppress those coupling errors? Because modulation itself adds complexity to the control pulse design.

Kai: Well, they show that for a thirty nanosecond gate duration, this detuning modulation strategy brings the coupling error down to six point two one times10-seven and it lets you tolerate coupling-strength uncertainties up to two pi times4 MHz while keeping the total gate infidelity under ten-three.

Mira: That's a pretty strong result for managing those off-diagonal errors, but what about those diagonal detuning errors, which are related to anharmonicities and qubit frequencies? They seem much harder to handle with that same technique.

Lev: I’ve seen that before; when you deal with the diagonal parameters, they tend to leak into the Hamiltonian channels in a way that makes them harder to suppress with simple dynamical decoupling.

Kai: That's why they suggest a different approach for those diagonal errors: operating near a symmetric-detuning operating point, where the detunings of both qubits are balanced.

Mira: So you’re trading off the coupling error suppression mechanism for this new constraint on the detuning? What does that symmetric point actually achieve in terms of minimizing those leakage-mediated interactions?

Lev: It helps balance those specific interactions between states like 1B1A and 0B2A, which are pretty tricky when you’re trying to keep fidelity high.

Kai: And for a twenty-four nanosecond gate, operating near that symmetric point, they tolerate individual uncertainties of up to two pi times5 MHz in each relevant diagonal parameter while still staying below the ten-three infidelity threshold.

Paper summary: Mira: So it seems like the trade-off is speed versus robustness; a longer gate at that symmetric point gives you more tolerance for those frequency drifts. But what’s the real hardware reality there?

Lev: On current systems, if we push for that twenty-four nanosecond window, we're fighting against energy relaxation <ref:2610.30681#pg1>. The paper explicitly says under present-day conditions, energy relaxation dominates, favoring a gate near the speed limit of twelve nanoseconds <ref:2610.30681#pg3,conditions, energy relaxation dominates, favoring a gate near the speed limit of>.

Kai: That makes sense because the intrinsic error reduction they show—finetuning within a five-level transmon model and Gaussian waveform filtering—gets the intrinsic error down to one point nine three times10-eight.

Mira: Even with that low intrinsic error, they still found that under present conditions, energy relaxation is still the main culprit limiting the total infidelity to about four point five five times10-six.

Lev: So what this means practically for running real hardware is that we have to decide when we stop optimizing for pure speed and start optimizing for robustness against parameter drift, which they suggest around twenty-four to twenty-eight nanoseconds <ref:2610.30681#pg3>.

Kai: Right, so the overall message of "High-fidelity and robust controlled-Z gates for superconducting transmon qubits. II. System-parameter uncertainties and overall errors" is that you can engineer control trajectories that are intrinsically less sensitive to parameter variations rather than relying only on a perfectly known nominal Hamiltonian.

Mira: It’s a practical way to improve the portability of pulse designs because the fidelity varies only weakly over experimentally relevant ranges of parameter deviations. This makes high-fidelity operation less dependent on those precise characterizations you mentioned earlier.

Lev: What this implies for scaling is that if we can build hardware that improves its coherence, we should transition our control strategies to these more robust ones sooner rather than later. It reduces the need for continuous cycles of measurement and recalibration across every gate in a large processor.

Kai: So the main point is balancing speed, fidelity, and robustness while reducing the need for exhaustive characterization in those large-scale superconducting quantum processors. We're looking at a modular framework that addresses both noise and parameter uncertainty simultaneously.

Mira: It’s about providing actionable guidance on when hardware improvements should be accompanied by a transition from speedoriented to robustness-oriented control, based on which error source—coupling or detuning—is dominant in the current stage of hardware performance.

Lev: I think the real hurdle moving forward is implementing those smooth single-shot flux pulses that achieve this, because getting those specific modulation patterns onto actual microwave pulses requires careful engineering and calibration.

Kai: So to wrap up, this paper gives us a unified way to design CZ gates that are intrinsically more resilient to parameter drift by using distinct suppression mechanisms for coupling errors and detuning errors. It’s a framework for making those gates work better when the hardware isn't perfect.

Conclusion: Kai: So, this paper is basically taking that control framework they built before and making it handle when your system parameters are drifting, not just when there’s random noise in it.

Mira: Yeah, they’re focusing on those two specific types of parameter uncertainty—the coupling strength stuff and the qubit frequencies—and showing how you can design gates that stay good even if those numbers aren't perfect.

Lev: For real hardware, that means we don't have to spend all day painstakingly tuning every single frequency before we can even start a gate sequence.

Kai: Exactly. They found two separate ways to fight the errors; one way for the coupling issues and another way for the detuning issues.

Mira: The main result is that you get these specific suppression mechanisms—like using detuning modulation for coupling errors, or operating at a symmetric point for detuning errors—and they each work on different types of imperfections.

Lev: I'm looking at the numbers here, and they're showing that with a thirty nanosecond gate, you can handle coupling uncertainty up to two pi times four MHz while keeping the total error below ten-three.

Kai: That’s a big number for robustness, it means we don't need perfect calibration every single time we run the experiment.

Mira: And for those diagonal detuning errors, they show that if you operate near that symmetric point, you can tolerate uncertainties of up to two pi times five MHz in each parameter if you keep the total infidelity below ten-three.

Lev: The caveat is that on current hardware, energy relaxation is still really pulling the total error up to about four point five five times ten-six for a twenty-four nanosecond gate.

Kai: So what this means for the future of building these machines is that we can stop chasing just raw speed and start designing gates that are actually more stable across different hardware stages.

Mira: It’s about providing a roadmap for engineers to know when they need to switch their control strategy from just making the pulse fast to making the pulse robust against parameter drift.

Chia-Hsien Huang, Hsi-Sheng Goan

Department of Physics and Center for Theoretical Physics, National Taiwan University · Center for Quantum Science and Engineering, National Taiwan University · Physics Division, National Center for Theoretical Sciences

quant-ph

Submitted: 2026-10-22

Updated: 2026-10-22

License: http://creativecommons.org/licenses/by/4.0/

Importance score: 92/100

The gist: My analysis combines all relevant information to construct a comprehensive, detailed summary, ensuring no critical technical nuance is overlooked.

Key concepts

Off-diagonal uncertainties: These errors relate to fluctuations in the coupling strengths between qubits. The framework addresses these by using dynamical decoupling through strong detuning modulation, which effectively cancels out the effects of varying coupling strengths, ensuring the gate remains accurate despite parameter drift.
Diagonal uncertainties: These errors stem from uncertainties in qubit frequencies and anharmonicities. These are controlled by operating near a symmetric-detuning point where the detunings of both qubits are balanced. This specific operating regime minimizes leakage-mediated interactions, thus making the gate less sensitive to frequency variations.
Dynamical Decoupling Modulation: This is a technique used to mitigate coupling errors. It involves rapidly modulating the detuning during the gate operation. This modulation acts as a noise filter, effectively suppressing errors caused by uncertainties in the off-diagonal coupling strengths, leading to significant error reduction.
Symmetric-Detuning Operating Point: This is a specific operating condition where the detunings of two qubits are nearly equal. By operating here, the framework balances different leakage interactions that cause diagonal errors. This balance ensures that the gate's performance remains stable even if individual qubit frequencies have small deviations.

Terminology

Fidelity — 1× in this paper · explained in 2 episodes
Transmon Qubit — 1× in this paper · explained in 3 episodes

Summary

My analysis combines all relevant information to construct a comprehensive, detailed summary, ensuring no critical technical nuance is overlooked.

Here is the detailed summary:

Comprehensive Summary of High-Fidelity and Robust Controlled-Z Gates Framework

This work presents a unified and highly robust optimal control framework designed to engineer high-fidelity controlled-Z (CZ) gates in superconducting transmon qubits, specifically addressing the challenges posed by both stochastic noise and systematic parameter uncertainties. The central goal is to develop gate operations that are intrinsically less sensitive to experimental fluctuations, thereby significantly reducing the need for exhaustive characterization and frequent recalibration, which is crucial for scaling up superconducting quantum processors.

Core Framework and Error Characterization

The research establishes a unified framework by combining noise-robust control strategies developed in a preceding work (Part I) with novel parameter-robust control strategies developed in the current study (Part II). This combination yields a CZ gate that is robust against both stochastic noise and parameter uncertainties.

The framework begins by rigorously formulating and quantifying CZ-gate errors arising from two primary sources of Hamiltonian parameter uncertainties:

Off-diagonal uncertainties: Perturbations to the off-diagonal coupling strengths (g AB).
Diagonal uncertainties: Perturbations to diagonal parameters, including anharmonicities (alpha A/alpha B) and zero-flux qubit frequencies (omega 0,A/omega 0,B).

The analysis reveals a critical decomposition: parameter uncertainties naturally separate into these two classes, which in turn dictate distinct error suppression mechanisms.

Distinct Error Suppression Mechanisms

The framework identifies and implements two distinct physical error-suppression mechanisms, tailored to the nature of each error class:

Mitigation of Coupling Errors (Off-diagonal Uncertainty):

This type of uncertainty is mitigated through dynamical decoupling induced by strong detuning modulation.
For a gate duration of 30 ns, this strategy successfully reduces the coupling error to 6.21 times 10-7, compared to 3.54 times 10-4 for conventional pulses without modulation.
This technique allows the gate to tolerate coupling-strength uncertainties up to plus or minus 2 pi times 4 MHz while maintaining a total gate infidelity below 10-3.

Mitigation of Detuning Errors (Diagonal Uncertainty):

Diagonal errors, such as those arising from anharmonicities and qubit frequencies, cannot be suppressed by the same dynamical decoupling mechanism because they enter through the same Hamiltonian channels as the controls themselves.
Instead, these errors are minimized by operating near a symmetric-detuning operating point, where delta A about delta B. This regime achieves balance between leakage-mediated interactions (specifically those involving 1B1A 0B2A and 1B1A 2B0A).
This symmetric operating point supports individual diagonal parameter deviations of up to plus or minus 2 pi times 5 MHz for a gate duration of 24 ns, while keeping the total infidelity below 10-3.

Stage-Specific Optimization and Performance Tracking

The framework is not static; it incorporates intrinsic dynamics, energy relaxation, dephasing, and parameter uncertainty across six representative stages of progressively improving hardware performance. The optimal control strategy is dynamically tracked for each stage based on the dominant error contributions at that point in the hardware evolution.

Intrinsic Error Reduction: At the most advanced stage considered (combining low decoherence with small parameter uncertainties), finetuning within a five-level transmon model and Gaussian waveform filtering reduces the **intrinsic error to 1.93 times 10-8 **.
Total Infidelity: The resulting total infidelity at this advanced stage is approximately ** 4.55 times 10-6 **, with the primary limiting factor being energy relaxation.
Robustness Trade-off: While energy relaxation favors a near-speed limit of 12 ns under present conditions, the framework suggests that robust gates with durations in the 24–28 ns range are preferable as coherence improves and parameter uncertainties become more significant contributors to total infidelity.

Principal Contributions and Practical Impact

The principal contributions of this work are threefold:

Error Formulation: Formulating and quantifying CZ-gate errors arising from both off-diagonal (coupling) and diagonal (detuning) Hamiltonian parameter uncertainties.
Mechanism Identification: Identifying two distinct physical error-suppression mechanisms—detuning-modulation-based dynamical decoupling for coupling errors, and operation near the symmetric-detuning point for diagonal errors—and incorporating them into smooth, experimentally realizable flux pulses.
Unified Stage-Specific Framework: Combining intrinsic, decoherence, and parameter uncertainty errors into a stage-specific framework that tracks the evolution of the optimal control strategy as hardware performance improves.

In summary, this research establishes a modular, unified framework for designing fast, high-fidelity, and robust CZ gates that accommodate both stochastic noise and parameter uncertainties. By engineering control trajectories intrinsically less sensitive to parameter variations and noise fluctuations rather than relying solely on precise nominal point optimization, the method substantially reduces calibration overhead and facilitates the practical operation of large-scale superconducting quantum processors. The resulting gate operations maintain accuracy over finite ranges of experimental variations, providing actionable guidance for adapting two-qubit control in advancing hardware architectures.

Improvements for AI systems

Robust control over coupling strength uncertainty can be achieved through dynamical decoupling induced by strong detuning modulation, which reduces coupling error to 6.21 × 10-7 for a 30-ns gate and tolerates coupling-strength uncertainties up to 2π × 4 MHz while maintaining total gate infidelity below 10-3.
Robust operation against diagonal parameter uncertainties is achieved by operating near a symmetric detuning point where the sensitivities of the relevant interactions are balanced, which allows for individual diagonal-parameter deviations of up to ±2π × 5 MHz for a 24-ns gate while keeping total infidelity below 10-3.
The AI system can be designed to select optimal gate durations and operating regimes based on hardware performance stages, allowing it to transition from speed-oriented control in early stages (like Stage 1) to robustness-oriented control in later stages (like Stage 6).
For a given set of noise and uncertainty conditions, the AI system can identify the most robust sample from an ensemble of optimized CZ gates by minimizing the infidelity at both positive and negative values of coupling constant uncertainty, leading to enhanced robustness against coupling strength variations.
The system can be tuned to find an optimal balance between noise sweet spots and detuning-error sweet spots by simultaneously varying the Josephson energy ratio aEJ and gate time tf, allowing it to adapt control settings for scenarios involving both flux noise and Rydberg-mediated error.
By incorporating realistic Hamiltonian simulations with single-qubit Z gate compensation, the AI system can accurately evaluate coupling errors by using the expression (I+ + I−)/2 − J1 to isolate the ensemble-averaged coupling error J2,gAB.

Abstract

In the companion paper (Part I), we developed an optimal-control framework to suppress intrinsic and decoherence-induced errors in controlled-Z (CZ) gates between directly coupled, frequency-tunable transmons. Here, we extend this framework to incorporate uncertainties in coupling strength, anharmonicities, and zero-flux qubit frequencies, enabling the design of high-fidelity gates robust against noise and parameter uncertainties. We classify these uncertainties by whether they perturb the off-diagonal coupling strengths or the diagonal detunings of the Hamiltonian, and we identify distinct suppression mechanisms for each class. Coupling errors are mitigated through dynamical decoupling induced by strong detuning modulation. For a 30-ns gate, this strategy reduces the coupling error to 6.21 times10-7 and tolerates coupling-strength uncertainties up to 2π times4 MHz while keeping total gate infidelity below 10-3. Detuning errors are minimized near a symmetric-detuning operating point that balances the two dominant leakage-mediated interactions. A 24-ns gate operated near this point tolerates individual uncertainties of up to 2π times5 MHz in each relevant diagonal parameter under the same infidelity threshold. We further optimize gate performance under realistic conditions where intrinsic errors, decoherence, and parameter uncertainties coexist across six representative stages of progressively improving hardware performance. The resulting stage-specific controls achieve lower infidelity and greater robustness. Together with the companion study (Part I), this framework offers a practical approach to balance speed, fidelity, and robustness while reducing the need for exhaustive characterization and frequent recalibration in large-scale superconducting quantum processors.

Sources

Millisecond-Scale Calibration and Benchmarking of Superconducting Qubits